Multiprocessing system configured to perform prefetch coherency

Details Multiprocessing system configured to perform prefetch coherency Multiprocessing system configured to perform prefetch coherency

1996-07-01

1999-03-09

Dinh, Dung C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39520043, 711137, 711146, G06F 1200, G06F 1300

Patent

active

058813039

ABSTRACT:
A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order presented by that subnode. Therefore, when a first transaction from the subnode is delayed to allow performance of coherency activity with other processing nodes, subsequent transactions from that subnode are delayed as well. Additionally, coherency activity for the subsequent transactions may be initiated in accordance with a prefetch method assigned to the subsequent transactions. In this manner, the delay associated with the ordering constraints of the system may be concurrently experienced with the delay associated with any coherency activity which may need to be performed in response to the subsequent transactions. In order to respect the ordering constraints imposed by the computer system, a system interface within the processing nodes employs an early completion policy for prefetch operations. If prefetch coherency activity for a transaction completes prior to coherency activity for another transaction from the same subnode, the early completion policy assigned to that transaction is enacted. In a drop policy, the data corresponding to the transaction is discarded. A write policy is also defined in which data received in response to the prefetch coherency activity is stored in the local memory. Lastly, a clear policy may be enforced in which the coherency activity is indicated to be complete.

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