Multiprocessing computer system employing capacity prefetching

Details Multiprocessing computer system employing capacity prefetching Multiprocessing computer system employing capacity prefetching

2007-01-16

2007-01-16

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

10408691

ABSTRACT:
Various embodiments of a multiprocessing computer system employing capacity prefetching are disclosed. In one embodiment, a cache subsystem implements a method for prefetching data. The method includes the cache subsystem receiving a request for data, and determining a cause of a cache miss that occurs in response to the request. The cache subsystem includes a controller that selectively prefetches additional data depending upon the cause of the cache miss. In one embodiment, determining the cause of the cache miss includes determining whether a cache line corresponding to the request exists in the cache memory of the cache subsystem in an invalid state. Additional data is prefetched in response to determining that the cache line is not present in the cache memory in an invalid state.

REFERENCES:
patent: 6119205 (2000-09-01), Wicki et al.
patent: 6128703 (2000-10-01), Bourekas et al.
patent: 6594730 (2003-07-01), Hum et al.
patent: 6665776 (2003-12-01), Jouppi et al.
patent: 6957306 (2005-10-01), So et al.
patent: 2002/0087802 (2002-07-01), Al-Dajani et al.

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