Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-10-23
2007-10-23
Ho, Tu-Tu (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S903000, C257SE27098, C365S230050
Reexamination Certificate
active
11192956
ABSTRACT:
A multiport memory cell (200, 300, 600) includes a first word line (WL1) coupled to a gate electrode of a first transistor (201, 301, 601). A second word line (WL2) is coupled to a gate electrode of a second transistor (202, 302, 602). Importantly, the memory cell (200, 300, 600) includes a conductive path (215, 315) between an electrically floating body (426) of the first transistor (201) and an electrically floating body (426) of the second transistor (202). The first word line (WL1) may overlie a first portion of a common body (426) and the second word line (WL2) may overlie a second portion of the common body (426). The common body (426) may be positioned vertically between a buried oxide layer (427) and a gate dielectric layer (430) and laterally between first and second source/drain regions (401, 407) formed in a semiconductor layer (425). The cell (200, 300, 600) may include a third transistor (603) including a third word line (613) where the shared transistor body (610) is shared with the third transistor (603) and wherein the conductive path is connected to the third transistor (603).
REFERENCES:
patent: 5939740 (1999-08-01), Hashimoto et al.
patent: 6613615 (2003-09-01), Mandelman et al.
patent: 6714436 (2004-03-01), Burnett et al.
patent: 6781875 (2004-08-01), Ohsawa
Sakurai et al., Transparent-Refresh DRAM (TReD) Using Dual-Port DRAM Cell, IEEE 1988 CICC; pp. 4.3.1-4.3.4.
Okhonin et al., A Capacitor-Less 1T-DRAM Cell, IEEE EDL, vol. 23, No. 2, Feb. 2002.
Burnett James D.
Hoefler Alexander B.
Clingan, Jr. James L.
Ho Tu-Tu
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