Multiport semiconductor memory device having RAM blocks and SAM

Details Multiport semiconductor memory device having RAM blocks and SAM Multiport semiconductor memory device having RAM blocks and SAM

1991-12-24

1994-06-07

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiple port access

36523004, 36523009, G11C 800

Patent

active

053196031

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device used for graphics which device is generally called a multiport video DRAM having a RAM and a SAM functioning as a serial register for the RAM.
The present invention relates also to the field of a computer graphics system, particularly to a device suitable for use as a frame buffer for storing image data and outputting the image data to a CRT.


BACKGROUND OF THE INVENTION

Recently, a multiport video RAM (MPRAM) has drawn attention as a memory suitable for high speed data processing and displaying in the fields of engineering work stations (EWS), computer graphics (CG), and the like. This MPRAM has a random access port (RAM port) having a memory array (e.g., DRAM) randomly accessible and a serial access port (SAM port) having a serial access memory cyclically and serially accessible.
In an MPRAM, data is transferred between the RAM port and SAM port. It is necessary to synchronize data transfer timings only during the transfer cycle. The timings during the transfer cycle will be described with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, there will be described the case wherein data at a certain row R in a memory array 101 of a RAM port is transferred to a serial access memory 102 having a SAM port which continuously executes serial access. In this case, an external signal DT for controlling transfer is first caused to fall (at time T1 in FIG. 1B). If the external signal DT takes an "L" level at the time when a signal RAS falls, then the transfer cycle starts. During this transfer cycle, similar to an ordinary RAM cycle, a row address and column address are supplied synchronously with the trailing edges of RAS and CAS (at times T2 and T3). The row address indicates a row of transfer data in the memory array 101, and different from an ordinary RAM cycle, the column address indicates a TAP address representative of the position of a new serial cycle after the data transfer. The transferred data is outputted starting from the TAP address at the serial cycle (time T6) after the external signal DT rises.
It is necessary for the external signal DT to rise at the timing (time T5) between the rising timing (time T4) and next rising timing (T6) of a serial clock signal SC. Therefore, time periods t1 (=T5-T4) and t2 (T6-T5) have some restriction. Such restriction of the time periods t1 and t2 is very severe for the application to practical products because the cycle time of the serial clock signal SC is 30 to 40 nsec.
In order to mitigate such restriction, a split transfer system has been proposed.
This split transfer system will be described with reference to FIGS. 2A and 2B. A serial access memory 102 having a SAM port to which the split transfer system is applied is divided into two groups of SAM (L) and SAM (U). The divided SAM (L) and SAM (U) correspond to "0" and "1" of the most significant bit (MSB) of the TAP address. It is therefore possible to transfer data from RAM 101 to SAM (L) and SAM (U) independently from each other. It is assumed that SAM (L) is now serially accessed. Consider the case wherein during this serial access a transfer cycle occurs, and the data at a row R of a memory array 101 having a RAM port is transferred to SAM 102. Similar to the case of FIG. 1A, the row address at this time indicates the row R. MSB of the TAP address is set to MSB (in this case "1") on the SAM side which is not now serially accessed. SAM for which transfer operation is carried out is SAM (U) with MSB set. The data transferred to SAM (U) is accessed starting from the TAP address with newly set MSB, when the serial access further continues and changes from SAM (L) to SAM (U). In the case shown in FIG. 2B, during the transfer cycle for the serial address 0 to 127, data in RAM 101 at the row R is transferred to SAM (U) at addresses 128 to 255. As the serial access advances to an address 127 and enters the next SC cycle, the TAP address is accessed to further continue the

REFERENCES:
patent: 5065368 (1991-11-01), Gupta et al.
patent: 5121360 (1992-06-01), West et al.

Affiliated with

Also associated with

Rating

Multiport semiconductor memory device having RAM blocks and SAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiport semiconductor memory device having RAM blocks and SAM , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiport semiconductor memory device having RAM blocks and SAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-798823