Multiport semiconductor memory device

Details Multiport semiconductor memory device Multiport semiconductor memory device

2007-08-21

2007-08-21

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000

Reexamination Certificate

active

11250407

ABSTRACT:
In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD−Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD−Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented.

REFERENCES:
patent: 6044034 (2000-03-01), Katakura
patent: 6711086 (2004-03-01), Terada
patent: 2004/0052147 (2004-03-01), McLaury
patent: 07-141859 (1995-06-01), None
Nii et al. “A 90 nm Dual-Port SRAM with 2.04 μ m28T-Thin Cell Using Dynamically-Controlled Column Bias Scheme.” IEEE ISSC Digest of Technical Papers, 27.9 Feb. 2004.

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