Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1994-12-30
2002-04-09
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S109000, C710S120000, C710S052000
Reexamination Certificate
active
06370623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of multiport register files for use in digital data processors.
2. Related Art
Multiport register files are used for digital data processors which need to access plural registers simultaneously. In particular, such register files are useful for VLIW (Very Long Instruction Word) processors. Such processors also include an instruction register accommodating plural operation codes and a plurality of functional units for executing the plural operations codes, starting simultaneously in a single machine cycle.
Multiport register files can be used in other types of processors as well.
A prior art multiport register file is shown in FIG.
1
. This file includes 128 32 bit registers.
To the left of the file are shown write address ports, WA
1
, WA
2
, and WA
3
, each being eight bits wide. Also shown on the left are write ports WD
1
, WD
2
, WD
3
, each being 32 bits wide. Results from 3 functional units can be written simultaneously on the write ports at the addresses specified on the write address ports.
To the right of the file are shown read address ports RA
1
, RA
2
, RA
3
, RA
4
, RA
5
, RA
6
, RA
7
, RA
8
, and RA
9
, each being eight bits wide. Also shown on the right are read ports, RD
1
, RD
2
, RD
3
, RD
4
, RD
5
, RD
6
, RD
7
, RD
8
, and RD
9
, each being 32 bits wide. Up to nine operands destined for the functional units can be read from this file simultaneously on the read ports from the addresses specified on the read address ports.
In VLIW processors, guard bits are used to condition writing of results from the functional units to the multiport register file. Guard bits become necessary in VLIW processors because of branching delays, as explained in U.S. application Ser. No. 594,534 filed Oct. 5, 1990. The functional units execute operations during a branch delay before the processor resolves whether results of those operations will actually be used. After the operations are completed, each functional unit will write results to the register file only if an associated guard bit has an appropriate value.
There are nine read ports in this particular file unit, because the VLIW processor in question has an instruction word accommodating 3 operations. Each operation will typically require two data operands and a guard bit. There are three write ports to accommodate a result from each of 3 simultaneously executing functional units. Each read or write port has an associated address port.
Ordinarily, the guard bits are to be supplied from the multiport register file. Guard bits, or multibit guard values, are generally much smaller than the thirty-two bit registers and thirty-two bit read and write ports available in the prior art register file. Where the writing from each functional unit is to be conditioned by a guard bit or value, a great deal of unnecessary circuitry is necessary, in particular extra 32-bit write and read port and extra 8-bit write and read address ports.
SUMMARY OF THE INVENTION
The object of the invention is to reduce circuitry necessary for operation of the multiport register file.
This object is achieved by dividing the multiport register file into two file units. The first file unit has wider registers than the second file unit.
Guard bits will be stored in the second file unit for VLIW processors. For other types of processors, other types of short data can be stored in the second file unit. Such short data can include flags, for example.
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Mehra Vijay K.
Slavenburg Gerrit Ary
Barschall Anne E.
Peikari B. James
Philips Electronics North America Corporation
Stephens Debra
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