Multiport memory with write priority detector

Details Multiport memory with write priority detector Multiport memory with write priority detector

1992-07-20

1994-02-22

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiple port access

365191, 36523006, G11C 800

Patent

active

052894274

ABSTRACT:
A write priority detector in a multiport memory prioritizes write operations to memory cell by activating one of its enable signals to a memory cell upon receiving multiple address signals at different write ports of the multiport memory, each attempting to access the same memory cell. The other enable signals are de-activated. One prioritization scheme provides first-come first-serve access to the memory cell among completing address signals. Alternately, a fixed priority scheme always gives one enable signal first priority.

REFERENCES:
patent: 4158235 (1979-06-01), Call et al.
patent: 4402067 (1983-08-01), Mass et al.
patent: 4752915 (1988-06-01), Suzuki et al.
patent: 5001671 (1991-03-01), Koo et al.
patent: 5014247 (1991-05-01), Albachten et al.
patent: 5042013 (1991-08-01), Sato
patent: 5060145 (1991-10-01), Scheuneman et al.

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