Multiport memory with test signal generating circuit controlling

Details Multiport memory with test signal generating circuit controlling Multiport memory with test signal generating circuit controlling

1991-06-10

1993-08-03

Heyman, John S.

Static information storage and retrieval

Addressing

Multiple port access

365201, G11C 700

Patent

active

052335640

ABSTRACT:
The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.

REFERENCES:
patent: 4731760 (1988-03-01), Maini
patent: 4833652 (1989-05-01), Isobe et al.
patent: 5109359 (1992-04-01), Sakakibara et al.

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