Multiport memory scheme

Details Multiport memory scheme Multiport memory scheme

1998-12-10

2001-11-20

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S185110, C365S189030, C365S230050

Reexamination Certificate

active

06320811

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memories generally and, more particularly, to a multiport memory scheme and writeable read only memories.
BACKGROUND OF THE INVENTION
Conventional approaches to implementing memories required the support circuitry to be duplicated for each memory. Such a duplication may be a limiting factor in small memories, such as those used with microprocessors. Additional real estate is required to duplicate the support circuitry to implement each memory.
FIG. 1
illustrates a memory array
10
illustrating one such conventional approach. The memory array
10
generally comprises an X-decoder and HV switch section
12
, an HV pump section
14
, a sense amplifier section
16
, a Y-selector section
18
and an array of memory cells
20
. For a 4k-byte EPROM, may be implemented using 128 rows of 256 columns of EPROM cells. The Y-selector
18
selects thirty-two columns into eight groups of outputs to achieve 1-byte of output. 7-bits of X-addresses are decoded to generate one of 128 wordlines. During a read operation, the wordlines are driven to zero volts, except for a one word line which is driven to the supply voltage Vcc. The sense amplifier
16
drives a current through one of thirty-two bit lines to sense the presence of the cell.
The erased cell has a threshold voltage Vtn of approximately 1.0 volts, while the program threshold voltage Vtn is approximately 6.0 volts (which is much greater than the supply voltage Vcc). Therefore, a program cell draws no current and the bit line will go to a high voltage while an erased cell will draw current and the first bit line will go to a low voltage. The sense amplifier
18
determines the difference as a data logic bit. A dummy PROM cell is always erased and hence acts as a current load reference to compare against.
During programming, the special circuitry drives the bit lines to a high voltage and the word line is driven to a voltage greater than the Vpp (approximately 14 volts). The X-decoders, the y-selector and sense amplifiers all must accommodate the extra stresses of high voltage programming. The overhead for this circuitry is very high for memories up to 32k bytes, which is typical to microcontrollers.
Conventional EPROM and E2PROM requires substantial extra circuitry that performs voltage boosting, high voltage switching and current sensing that normally accounts for about 50% or more of the overall area when PROMS are built. Therefore, if two PROMS are used on the same die, one usually pays this overhead twice in some form. Some conventional approaches use the high voltage generators for each of the PROMS, but do not generally use other support circuitry.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a memory array having a first region, a second region, a plurality of bitlines and an X-decoder. A plurality of transistors may each coupled between the first and second regions, where each of the transistors may be configured to (i) separate the first and the second region during a read operation and (ii) join the first and the second region during a write operation. Alternatively, a plurality of memory regions may be implemented, each separated by another plurality of transistors.
The objects, features and advantages of the present invention include providing a memory that splits the bitlines into two or more partitions that may be used to generate separately memory addressable sections that can share a number of common support circuitry components. The present invention may share the overhead between two PROMS by building a single ROM with two distinct memories.


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patent: 5930168 (2000-10-01), Roohparvar
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