Multiport memory device and an operation method thereof

Details Multiport memory device and an operation method thereof Multiport memory device and an operation method thereof

1992-10-02

1995-01-24

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365195, 36523005, G11C 700

Patent

active

053847342

ABSTRACT:
Memory cell array includes a plurality of 2-port memory cells. A first row address decoder for decoding a first address signal to select a first word line included in any one of a plurality of word line groups, and a second row address decoder for decoding a second address signal to select a second word line included in any one of a plurality of word line groups are provided. A word line driving circuit receives output signals of first and second row address decoders to drive first and second word lines in accordance with a predetermined inhibit condition.

REFERENCES:
patent: 4554645 (1985-11-01), Furman
patent: 4742487 (1988-05-01), Bernstein
patent: 5036491 (1991-07-01), Yamaguchi
patent: 5073873 (1991-12-01), Nogami
Bliklen, "Speicherkonfigurationen mit Dual-Port SRAMs", Design & Elektronik, 12th issue, Jun. 9, 1987, 99. 106, 108.

Affiliated with

Also associated with

Rating

Multiport memory device and an operation method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiport memory device and an operation method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiport memory device and an operation method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1472436