Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-07-15
2002-11-12
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S149000, C365S219000, C365S233100
Reexamination Certificate
active
06480947
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique capable of utilizing a plurality of RAMs as a single multiport memory apparently, and to a technique effective for application to, for example, a multiport memory, and a data processor or the like called a microcomputer or a microprocessor or the like.
The present inventors have discussed multiporting of a semiconductor memory. For example, memory cells of a multiport memory capable of parallel access completely in theory are respectively provided with data input/output terminals and memory-cell selection terminals by the number of ports. Thus, bit lines and word lines are provided as plural pairs and transistors for selecting the memory cells are provided every pairs of the respective bit lines and word lines. Therefore, when the numbers of the word lines and the bit lines increase according to the required number of ports, each memory chip greatly increases in area. There is also an increasingly fear of the occurrence of a malfunction due to crosstalk or the like that occurs between the adjacent bit lines. As a result, limitations are spontaneously placed on an increase in the number of ports in a single memory.
Thus, a multiport RAM can be apparently constructed using a plurality of RAMS. This technique has been described in Japanese Patent Application Laid-Open No. Hei 1-251387 (1989). When, for example, two two-port RAMs having parallel accessible write and read ports are used so as to constitute a single three-port RAM apparently, the same data must be written into the two two-port RAMs upon data writing. Therefore, the write ports of the two two-port RAMs are connected in common as one port. Similarly, even when n (n: integer greater than or equal to 3) pieces of the two-port RAMs are used to constitute a multiport memory having n+1 ports apparently, write ports of the n two-port RAMs must be connected in common. Such a multiport RAM cannot perform a parallel write access to different data upon writing but is able to perform a parallel read access to n different data with respect to n ports upon reading. However, a problem arises in that since the number of memory chips activated in parallel according to the required number of ports, the amount of power consumption will increase.
On the other hand, the present inventors have previously filed the invention about the multiporting (see U.S. Pat. No. 5,422,858 (Jun. 6, 1995)). According to this, a speed or rate converter for converting each address or data into parallel/serial form and interfacing to the outside is provided at an access port of each memory to thereby set an internal memory access rate to, for example, twice an external access rate, whereby a single-port RAM is accessible as a dual-port RAM apparently. According to this construction, even if the number of memories is not increased, the apparent number of ports can be increased by a logical configuration of the rate converter as in the case of an increase in the apparent number of multiport or multiple ports with respect to one port, e.g., four ports and eight ports.
SUMMARY OF THE INVENTION
Since RAMs are serially activated to increase the number of multiport or multiple ports apparently when the rate converter is used, the number of the RAMs to be activated in parallel can be reduced, thereby making it possible to contribute to low power consumption as compared with the prior art. However, the present inventors have revealed the problem that when the apparent number of multiport or multiple ports is increased without an increase in the number of the memories, a time interval required to determine all the data read from all the read ports increased apparently is delayed with the increase in the apparent number of multiple ports from the relationship in which actual accesses to the memories are serially performed.
An object of the present invention is to provide a multiport memory capable of contributing to low power consumption and improving a delay in apparent parallel read access even if the number of multiport or multiple ports apparently increases.
Another object of the present invention is to allow the implementation of a single multiport memory by using general-purpose memory chips, and to provide a data processor capable of providing low power consumption for the implemented multiport memory and improving a delay in apparent parallel read access even when the apparent number of multiport or multiple ports increases.
A further object of the present invention is to reduce the cost of a data processing system using a multiport memory and the amount of power consumption thereof.
The above and other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
REFERENCES:
patent: 5422858 (1995-06-01), Mizukami et al.
patent: 1-251387 (1989-10-01), None
Hasegawa Masami
Iioka Yoshio
Kitagawa Yoshimi
Satoh Yoichi
Uchida Makio
Moazzami Nasser
Yoo Do Hyun
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