Multiport memory collision/detection circuitry

Details Multiport memory collision/detection circuitry Multiport memory collision/detection circuitry

1989-10-10

1991-10-29

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

Multiple port access

36523002, 3652335, 36518904, G11C 700, G11C 800, G11C 11418

Patent

active

050620819

ABSTRACT:
A multiport memory system is provided with a collision detection system to prevent collision between information which is simultaneously being read to a particular memory row and information being written to that same memory row simultaneously. Memory rows of the multiport memory system are independently addressed by address signals for a first port and by address signals corresponding to a second port. Row select signals are generated from the address signals of each of the ports when the row select signals for one particular memory row of the memory array are simultaneously present a match signal is generated. The match signal controls a forwarding logic circuit which connects the write port information directly to the read port when a match is present, providing immediate access to the most current information being written into the memory array. A write-strobe signal for entering information into the multiport memory array memory cells is provided for gating the match signal to provide a forward signal for the system.

REFERENCES:
patent: 4623990 (1986-11-01), Allen et al.
patent: 4660177 (1987-04-01), O'Connor
patent: 4663742 (1987-05-01), Andersen et al.
patent: 4719596 (1988-01-01), Bernstein et al.
patent: 4742493 (1988-05-01), Lewallen et al.
patent: 4891788 (1990-01-01), Kreifels

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