Multiport memory

Details Multiport memory Multiport memory

2007-07-03

2007-07-03

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S189011, C365S194000

Reexamination Certificate

active

11184926

ABSTRACT:
This multiport memory has a memory hold circuit, a plurality of write circuits and read circuits, and a read/write capability regulating circuit. The read/write capability regulating circuit individually sets a write/read capability of each of the write/read circuits. The read/write capability regulating circuit determines, using an operating state determining circuit, the number of writing/reading times per unit time in accordance with an operating state of each of the read/write circuits. As the operating state determining circuit used is a noise amount detection circuit, an operation completion detecting circuit, or a potential fluctuation detecting circuit.

REFERENCES:
patent: 6400597 (2002-06-01), Nagaoka
patent: 6538933 (2003-03-01), Akioka et al.
Klein, et al., “350 MHz Time-Multiplexed 8-port SRAM and Word-Size Variable Multiplier for Media Processor”, The Institute of Electronics, Information and Communication Engineers, pp. 57-64, Mountain View, CA, (w/English Translation, pp. 1-4).

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