Multiport memory

Details Multiport memory Multiport memory

1993-09-16

1994-12-27

Popek, Joseph A.

Static information storage and retrieval

Addressing

Multiple port access

36518905, 365194, 365221, G11C 700, G11C 800

Patent

active

053771575

ABSTRACT:
A multiport memory comprises a pair of memory cells, at least a pair of bit line and a pair of word lines on a random access port side. One of the memory cell is connected to one bit line and one word line and the other memory cell is connected to the other bit line and the other word line. A pair of data lines which are respectively connected to load elements are also provided in the random access port side of the multiport memory. A first switch circuit is connected between the pair of bit lines and the pair of data lines. On a serial access port side, a data register is connected between the pair of bit lines to receive data transmitted through the pair of bit lines. A second switch circuit for transmitting data is connected between the pair of bit lines and the data register. A control circuit opens the first switch circuit, before closing the second switch circuit to transmit data stored in the memory cells to the data register.

REFERENCES:
patent: 4858190 (1989-08-01), Yamaguchi et al.
patent: 5138581 (1992-08-01), Miyamoto et al.
patent: 5247484 (1993-09-01), Watanabe
patent: 5249165 (1993-09-01), Toda

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