Multiport FIFO with programmable width and depth

Details Multiport FIFO with programmable width and depth Multiport FIFO with programmable width and depth

2000-03-22

2003-02-25

Verbrugge, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

Reexamination Certificate

active

06526495

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multiport FIFOs generally and, more particularly, to a multiport FIFO with programmable width and depth.
BACKGROUND OF THE INVENTION
Conventional approaches for implementing multi-queue buffering systems may implement multiple discrete FIFOs. Different applications may require discrete FIFOS with different depths and widths.
Implementing multiple FIFOs may require larger board area (e.g., due to multiple discrete packages and more complex routing), higher power consumption, longer trace lengths, and potentially higher cost (e.g., due to many discrete devices being used, as well as the cost of inventorying devices of differing widths and depths), than a single FIFO implementation.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a memory array and a control circuit. The memory array generally comprises a plurality of storage queues. Each of the storage queues may be configured to (i) receive and store an input data stream and (ii) present an output data stream. The storage queues may be configured to operate either (i) independently or (ii) in combination, to store the input data streams, in response to one or more control signals. The control circuit may be configured to present the one or more control signals to control an operation of the plurality of storage queues. The control signals may be configured to control the configuration of the plurality of storage queues.
The objects, features and advantages of the present invention include providing a multiport FIFO that may implement (i) a configurable number of queues within the same memory device, (ii) multiple ports available on the device for simultaneous access to multiple queues, (iii) configurable depth and width of the multiport FIFO, (iv) flag logic block that may be disabled or enabled and/or (v) a special case of device operation where only one input and output port is implemented, yet data can be stored into multiple, selectable FIFO queues.


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