Multiport DRAM

Details Multiport DRAM Multiport DRAM

1992-04-08

1993-09-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiple port access

36523003, 36523009, 365239, G11C 700

Patent

active

052474844

ABSTRACT:
A plurality of RAM blocks constituting a first RAM section and a second RAM section, respectively are arranged alternately in such a way that the inversion bit lines and the non-inversion bit lines of these RAM blocks are changed alternately block by block and further the two adjacent bit lines of the two adjacent RAM blocks are connected in common as a data line of the SAM blocks. By controlling data transfer control gates for switching on-off conditions of four bit lines of the two adjacent RAM blocks, it is possible to realize a cross transfer such that data can be transferred not only from the RAM blocks of the first RAM section and the second RAM section to the first SAM section and the second SAM section disposed as to correspond to the RAM sections, respectively, but also from the RAM blocks of the first RAM section to the SAM blocks of the adjacent second SAM section and additionally from the RAM blocks of the second RAM section to the RAM blocks of the adjacent first SAM section. Therefore, it is possible to continuously read and write data from and to the same RAM block, in addition to the alternate data read and write operation between the RAM blocks.

REFERENCES:
patent: 4891794 (1990-01-01), Hush et al.
patent: 4930108 (1990-05-01), Sugiyama
patent: 5051954 (1991-09-01), Toda et al.
patent: 5065369 (1991-11-01), Toda
patent: 5121360 (1992-06-01), West et al.

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