Multiplying phase detector for use in a random data locked...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S376000

Reexamination Certificate

active

07142622

ABSTRACT:
A multiplying phase detector includes a 1stmultiplier, a 2ndmultiplier and a phase error generation module. The 1stmultiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1stclock, which is in-phase with the incoming stream of data and is one-half the rate of the incoming stream of data, to produce a 1stproduct. In this instance, the 1stproduct represents missing transitions in the incoming stream of data. The 2ndmultiplier is operably coupled to multiply the 1stproduct with the incoming data stream to produce a modified stream of data. The phase error generation module is operably coupled to generate a phase error based on the modified stream of data and a 2ndclock, where the phase error represents a phase offset between the modified stream of data and the 2ndclock.

REFERENCES:
patent: 4320345 (1982-03-01), Waggener
patent: 6411661 (2002-06-01), Nguyen et al.
patent: 6603803 (2003-08-01), Hatch
patent: 2002/0048107 (2002-04-01), Bryant et al.
patent: 2004/0202266 (2004-10-01), Gregorius et al.

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