Multiplying digital-to-analog converters and methods that...

Details Multiplying digital-to-analog converters and methods that... Multiplying digital-to-analog converters and methods that...

1998-10-06

2001-07-10

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S172000

Reexamination Certificate

active

06259392

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to digital-to-analog converters and converting methods, and more particularly to multiplying digital-to-analog converters and methods and pipelined analog-to-digital converters and methods using the same.
BACKGROUND OF THE INVENTION
Multiplying Digital-to-Analog Converters (MDAC) and converting methods are widely used in electronic systems to multiply an analog input signal at an analog input terminal and a digital input signal at a digital input terminal, to produce an analog output signal at an analog output terminal. For example, MDACs are widely used as a component of a pipelined analog-to-digital converter (ADC). As is well known to those having skill in the art, a pipelined ADC employs a plurality of MDACs that are serially connected, such that the analog output terminal of a preceding MDAC is connected to the analog input terminal of a succeeding MDAC. A pipelined ADC also uses a plurality of ADCs, a respective one of which is connected between the analog input terminal and the digital input terminal of a respective one of the MDACs. Pipelined ADCs are widely used, for example for high-speed data processing in high definition television, image recognition, radar and medical instrument systems.
Unfortunately, it may be difficult to match the various elements of a pipelined ADC in order to maintain a high degree of linearity. In order to match these elements, self-calibration, error averaging and laser trimming techniques have been employed in the design and manufacture of pipelined ADCs. Notwithstanding these developments, linearity may continue to be a problem in pipelined ADCs.
Referring now to
FIG. 1
, a pipelined ADC
100
comprises MDACs
110
,
130
and
150
, ADCs
120
,
140
,
160
and
180
, and a correction and data output circuit
190
that corrects the data output from the ADCs
120
,
140
,
160
,
180
to generate the corrected digital output data DO. An external analog signal AI
1
is input to the first ADC
120
and to the first MDAC
110
. The first ADC
120
converts the external analog signal AI
1
into first digital data DDI
1
that is applied to the first input d
1
of the correction and data output circuit
190
and to the first MDAC
110
. The first MDAC
110
amplifies the difference between the external analog signal AI
1
and the first digital data DDI
1
to generate a first multiplied analog signal AI
2
.
Similarly, the multiplied analog signal AI
2
is input to the second ADC
140
and to the second MDAC
130
. The second ADC
140
converts the first multiplied analog signal AI
2
into second digital data DDI
2
that is applied to the second input d
2
of the correction and data output circuit
190
and to the second MDAC
130
. The second MDAC
130
amplifies the difference between the first multiplied analog signal AI
2
and the second digital data DDI
2
to generate a second multiplied analog signal AI
3
.
Likewise, the second multiplied signal AI
3
is input to the third ADC
160
and to the third MDAC
150
. The third ADC
160
converts the second multiplied analog signal AI
3
into third digital data DDI
3
that is applied to the third input d
3
of the correction and data output circuit
190
and to the third MDAC
150
. This third MDAC
130
amplifies the difference between the second multiplied analog signal AI
3
and the third digital data DDI
3
to generate a third multiplied analog signal AI
4
that is applied to the fourth ADC
180
. The fourth ADC
180
converts the third multiplied analog signal AI
4
into fourth digital data that is applied to the fourth input d
4
of the correction and data output circuit
190
. Finally, the correction and data output circuit
190
corrects the second to fourth digital data received through the second to fourth inputs d
2
to d
4
based on the first digital data received through the first input d
1
, to generate the digital output data DO.
Referring to
FIG. 2
, an N-bit MDAC
120
-
180
that can be used in a pipelined ADC as shown in
FIG. 1
, comprises a plurality of switches, a capacitor array and an operational amplifier. When a first clock pulse is generated, the MDAC samples the analog input signal to the capacitors. When a second clock pulse is generated, the switches are selectively connected to the reference voltage Vref, the feedback line F/B or ground GND according to the digital data obtained from the input analog signal, to amplify the residue voltage which is the difference between the values of the analog signal and the digital data. The MDAC may employ a fixed feedback capacitor and/or a rearrangement feedback capacitor. The MDAC shown in
FIG. 2
employs both fixed feedback capacitors and rearrangement feedback capacitors. Such a pipelined ADC is disclosed in an article entitled “Pipelined A-D Conversion Technique with Near-Inherent Monotonicity”, IEEE Vol. 42, pp. 500-502, July 1995, the disclosure of which is hereby incorporated herein by reference.
The conventional MDAC uses two fixed feedback capacitors C
7
and C
8
. Reference symbol C represents a unit capacitor. Vref represents a first reference voltage and GND represents a second reference voltage such as ground voltage. The analog input signal corresponds to digital data from 000 to 111. This MDAC structure establishes a code pattern, as shown in
FIGS. 3 and 4
, which includes 4 nominal ranges and 4 error correction ranges (2 add ranges and 2 subtract ranges) to correct the errors occurring in the other flash ADC blocks. Hence, it is possible to correct the errors with over 4 bits precision in the flash blocks.
In such an MDAC, the overall errors that may occur due to the capacitor error are expressed by means of Vdrop (generally 1-2 V
ref
), and the linearity difference is expressed by DNL (Differential Non-Linearity) in the following Equations, which represent the values of the Vdrops in the transition from 000 to 111. In the Equations, V
1
represents a residue peak voltage, and V
2
represents a residue bottom voltage. Vdrop represents the difference between V
1
and V
2
, i.e., the residue drop.
C
T
={fraction (1/9)}(
C
0
+C
1
+C
2
+C
3
+C
4
+C
5
+C
6
+C
7
+C
8
)  (1)
 
C
i
=C
(1+&egr;
i
),
I=
0, 1, 2, . . . , 8  (2)
V
1
=
8
⁢
C
C
⁡
(
2
+
ϵ
7
+
ϵ
8
)
×
Vref
8
=
Vref
2
+
ϵ
7
+
ϵ
8
⁢
 
(
3
)
V
2
=
8
⁢
C
2
+
ϵ
8
+
ϵ
7
×
Vref
8
-
1
+
ϵ
0
2
+
ϵ
8
+
ϵ
7
⁢
Vref
=
-
ϵ
0
⁢
Vref
2
+
ϵ
8
+
ϵ
7
⁢
 
(
4
)
V
drop
=
V1
-
V2
=
Vref
2
+
ϵ
8
+
ϵ
7
-
-
ϵ
0
⁢
Vref
2
+
ϵ
8
+
ϵ
7
=
(
1
+
ϵ
0
)
⁢
Vref
2
+
ϵ
8
+
ϵ
7
=
1
2
⁢
(
1
+
ϵ
0
-
1
2
⁢
ϵ
8
-
1
2
⁢
ϵ
7
)
⁢
Vref
(
5
)
This MDAC can also employ a rearrangement feedback capacitor without using a fixed feedback capacitor, to produce a code pattern as shown in FIG.
5
. The error Vdrop of such structure may be obtained by the following Equations:
V
1
=
8
⁢
C
C
⁡
(
1
+
ϵ
1
)
×
1
8
⁢
Vref
=
1
1
+
ϵ
2
⁢
Vref
⁢
 
(
6
)
V
2
=
Vref
C
⁡
(
1
+
ϵ
2
)
-
C
⁡
(
1
+
ϵ
1
)
C
⁡
(
1
+
ϵ
2
)
⁢
Vref
=
-
ϵ
1
1
+
ϵ
2
⁢
Vref
⁢
 
(
7
)
V
drop
=
V
1
-
V
2
=
Vref
1
+
ϵ
1
+
ϵ
1
1
+
ϵ
2
⁢
Vref
=
Vrefx
⁢
1
+
ϵ
2
+
ϵ
1
+
ϵ
1
2
1
+
ϵ
1
+
ϵ
2
+
ϵ
1
⁢
ϵ
2
=
Vref
⁡
(
1
+
ϵ
1
2
-
ϵ
1
⁢
ϵ
2
)
(
8
)
According to Eq. 5, the primary error factor &egr;
0
is eliminated but the secondary error factor may not be eliminated. Constructing a pipelined ADC by using such MDAC structure, the code pattern proceeds as shown in FIG.
6
. This results in 8 nominal ranges with 2 error correction ranges (1 add

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