Multiply accumulate computation unit

Details Multiply accumulate computation unit Multiply accumulate computation unit

1996-08-27

1998-08-18

Elmore, Reba I.

Boots, shoes, and leggings

G06F 700

Patent

active

057966451

ABSTRACT:
A multiply/accumulate computation circuit is provided. The circuit will perform the multiplication of a first binary number that is a multiplicand and a second binary number that is a multiplier to produce a product. The product can be added or subtracted from a previous result. The product may be negated. The product may be multiplied by a factor of two. Or the product that is multiplied by the factor of two may be added or subtracted from the previous result. The multiplication is accomplished in a modified Radix 4 Booth's encoding and translation circuit to produce a set of partial products that are combined in a n operand adder to form a final result.

REFERENCES:
patent: 4575812 (1986-03-01), Kloker et al.
patent: 5497342 (1996-03-01), Mou et al.
patent: 5500812 (1996-03-01), Saishi et al.
C.S. Wallace, "A Suggestion For A Fast Multiplier" IEEE Transaction on Computers vol. 13, pp. 14-17, Feb. 1964.
A.D. Booth, "A Signed Binary Multiplication Technique" Quarterly Journal of Mechanical and Applied Mathematics, vol. 4, p. 42, 1951, pp. 236-240.

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