Multiplier speed improvement by skipping carry save adders

Details Multiplier speed improvement by skipping carry save adders Multiplier speed improvement by skipping carry save adders

1982-12-15

1985-12-03

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 752

Patent

active

045569487

ABSTRACT:
A complement carry technique and a staged skipping technique are employed for multipliers using four or more stages of carry save adders, to allow slower bits to skip past a stage while faster bits must go through that stage, thereby speeding up the multiplier's overall speed of operation. The complement carry technique minimizes hardware by allowing sums and carries to be generated by the carry save adders in either a true or a complement form. The skip technique takes advantage of the fact that the generation of a carry bit is faster than the generation of a sum bit. In the case of a four stage carry save adder designed for a multiplier, the skip technique reduces the number of circuit delays from the existing eight to the improved seven, without the addition of any hardware. Thus, the technique can result in a speed improvement for a multiplier.

REFERENCES:
patent: 3515344 (1970-06-01), Goldschmidt et al.
patent: 3761698 (1973-09-01), Stephenson
patent: 4052604 (1977-10-01), Maitland et al.
patent: 4218747 (1980-08-01), Miura
Wallace, "A Suggestion for a Fast Multiplier", IEEE Trans. on Electronic Computers, Feb. 1964, pp. 14-17.
Partridge, "Cascade Adder for Multiply Operations", IBM Tech. Disclosure Bulletin, vol. 13, No. 8, Jan. 1971, pp. 2406-2407.
Lai et al, "Logic Networks of Carry-Save Adders", IEEE Trans. on Computers, vol. C-31, No. 9, Sep. 1982, pp. 870-882.
J. P. Beraud, "High Speed Four-Bit Adder", IBM TDB, 5/1974, p. 3950.

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