Multiplexing of trim outputs on a trim bus to reduce die size

Details Multiplexing of trim outputs on a trim bus to reduce die size Multiplexing of trim outputs on a trim bus to reduce die size

1998-06-30

2001-07-10

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S185010, C365S185290, C365S185330, C365S189011

Reexamination Certificate

active

06260104

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to static information storage and in particular the present invention relates to multiplexing trim circuits.
BACKGROUND OF THE INVENTION
Many processor systems which operate with an associated memory require a particular memory configuration to operate properly. By way of example, some systems require a word length of eight bits and some require sixteen bits. There are conventional memory systems available which permit the end user to control the word size to some degree. However, this somewhat increases the complexity imposed upon the end user of the memory since the end user must provide the necessary signals to the memory for controlling the word length. As a further example, most processor systems look to a certain portion of a memory for boot data at power on. Such boot data is necessary for the processor to function in a system. The processor will be implemented to expect the boot data to be at a specific memory address. Some processors expect the boot data to be at the memory low addresses (bottom boot) and some processors expect the boot data to be at the memory high addresses (top boot). In order to provide capabilities for different types of processor systems, it is possible to produce a different memory system for each application. However, it is always desirable to limit the number of different memory types which must be manufactured.
It is desirable to have a memory system which can be fully characterized after fabrication. See for example U.S. Pat. No. 5,627,784 entitled “Memory System Having Non-Volatile Data Storage Structure for Memory Control Parameters and Method” which is incorporated herein for a description of a memory which uses non- volatile data storage units for controlling parameters of the memory device. These non- volatile data storage units are typically located in a common area on the integrated circuit and are coupled to circuitry which is located throughout the integrated circuit. The interconnect system is both complex and requires substantial die area.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory which uses data storage units for controlling parameters of the memory device and reduces die area by multiplexing control signals.
SUMMARY OF THE INVENTION
The above mentioned problems with routing control signals and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In particular, the present invention describes an integrated circuit comprising trim circuitry which provides output signals to control operations of internal circuitry. The trim circuitry includes a plurality of non-volatile fuse adapted to provide X trim signals. A trim bus is selectively coupled to the trim circuitry for routing the X trim signals across the integrated circuit. The trim bus comprises Y interconnect lines, where Y is greater than X. Multiplex circuitry is provided for coupling a group of Y trim signals selected from the X trim signals of the trim circuitry to internal circuits via the trim bus.
Another aspect of the invention provides a flash memory device comprising trim circuitry which provides output signals to control operations of internal circuitry. The trim circuitry includes a plurality of non-volatile memory cells adapted to provide X trim signals. A trim bus is selectively coupled to the trim circuitry for routing the X trim signals across the flash memory device, the trim bus comprising Y interconnect lines, where Y is greater than X. Further, multiplex circuitry is provided for coupling a group of Y trim signals selected from the X trim signals of the trim circuitry to internal circuits via the trim bus.


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patent: 6011418 (2000-01-01), Siniscalchi

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