Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2006-12-12
2008-10-21
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S037000, C326S047000
Reexamination Certificate
active
07439774
ABSTRACT:
Disclosed herein is a multiplexing circuit for decreasing the output delay time of an output signal. The multiplexing circuit includes multiplexing units and a multiplexing output unit. Each multiplexing unit is initialized in response to an initialization signal, and outputs an input signal as a selection output signal in response to a selection control signal. The multiplexing output unit performs a logic operation on selection output signals received from the multiplexing units and outputs a multiplexing output signal based on the results of this operation. Preferably, the initialization signal is shared by two of the multiplexing units, and the initialization signal which is input to one of the two multiplexing units is the selection control signal which in input to the other of the two multiplexing units.
REFERENCES:
patent: 5625303 (1997-04-01), Jamshidi
patent: 6031401 (2000-02-01), Dasgupta
patent: 7138833 (2006-11-01), Tanaka
patent: 08/111632 (1996-04-01), None
patent: 1020050113000 (2005-12-01), None
Rhyne, Fundamentals of Digitals Systems Design, 1933, N.J., pp. 70-71.
Hynix / Semiconductor Inc.
Lowe Hauptman & Ham & Berner, LLP
Tran Anh Q
LandOfFree
Multiplexing circuit for decreasing output delay time of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiplexing circuit for decreasing output delay time of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplexing circuit for decreasing output delay time of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4011464