Multiplexer having a plurality of internal data paths that opera

Details Multiplexer having a plurality of internal data paths that opera Multiplexer having a plurality of internal data paths that opera

1995-09-27

1997-04-29

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326108, 326113, 327408, H03K 19084, H03K 19094

Patent

active

056253036

ABSTRACT:
A multiplexer. The multiplexer comprises a first data input and a second data input coupled to a logic gate via a first data path and a second data path, respectively, wherein a maximum of one of the first and second data paths is enabled to pass data at any given time. The data paths are independent of one another such that devices of the first data path do not load the second data path, and vice versa. The speed of a data path is determined by how many data input signals are routed through the same data path. In this manner, the speed of each data path may be tuned as required to provide the necessary operating speeds.

REFERENCES:
patent: 4985703 (1991-01-01), Kaneyama
patent: 5126596 (1992-06-01), Millman
patent: 5162666 (1992-11-01), Tran

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