Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1998-08-04
2000-08-01
Tokar, Michael
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 39, 326 41, 326 38, 326 40, G01N 3300
Patent
active
060972106
ABSTRACT:
An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.
REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 3849760 (1974-11-01), Endou et al.
patent: 4750155 (1988-06-01), Hsieh
patent: 4821233 (1989-04-01), Hsieh
patent: 4831586 (1989-05-01), Nakagawa et al.
patent: 5208781 (1993-05-01), Matsushima
patent: 5272672 (1993-12-01), Ogihara
patent: 5381058 (1995-01-01), Britton et al.
patent: 5394031 (1995-02-01), Britton et al.
patent: 5426379 (1995-06-01), Trimberger
patent: 5457408 (1995-10-01), Leung
patent: 5485418 (1996-01-01), Hiraki et al.
patent: 5488582 (1996-01-01), Camarota
patent: 5528170 (1996-06-01), Britton et al.
patent: 5638315 (1997-06-01), Braceras et al.
patent: 5670897 (1997-09-01), Kean
patent: 5773993 (1998-06-01), Trimberger
"The Programmable Logic Data Book", published Jul. 1996, by Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 4-54 to 4-78.
"The Programmable Logic Data Book", 1993, published by Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 8-17 to 8-24.
Iwanczuk Roman
Schultz David P.
Young Steven P.
Cartier Lois D.
Hoffman, Esq E. Eric
Tan Vibol
Tokar Michael
Xilinx , Inc.
LandOfFree
Multiplexer array with shifted input traces does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiplexer array with shifted input traces, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplexer array with shifted input traces will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-667493