Multiplexed serial register architecture for VRAM

Details Multiplexed serial register architecture for VRAM Multiplexed serial register architecture for VRAM

1989-12-05

1991-01-08

Popek, Joseph A.

Static information storage and retrieval

Addressing

Multiple port access

36523002, G11C 700, G11C 800

Patent

active

049842145

ABSTRACT:
A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

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