Multiplexed random access memory with time division multiplexing

Details Multiplexed random access memory with time division multiplexing Multiplexed random access memory with time division multiplexing

1996-03-11

1998-10-13

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711211, 395287, 395878, 395894, G06F 1320

Patent

active

058227768

ABSTRACT:
A multiported random access memory (RAM) system comprising a RAM having a data port and an address and control port, plural data buffers each having a bidirectional input port and a bidirectional output port, a data bus connecting the output ports of the data buffers and the data port of the RAM, a multiplexer having plural address and control inputs and an address and control output, the address and control output being connected to the address and control port of the RAM, each of the address and control inputs for receiving address and control data associated with data stored in a specific buffer, a timing apparatus connected to each of the buffers and to a control input of the multiplexer for separately enabling the multiplexer to pass address and control data therethrough to the address and control port of the RAM or to receive data from the data port of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports forms a separate time shared port to the RAM.

REFERENCES:
patent: 3828320 (1974-08-01), Dinerman et al.
patent: 4164787 (1979-08-01), Aranguren
patent: 4539656 (1985-09-01), Abrant
patent: 4562572 (1985-12-01), Goldman et al.
patent: 4837785 (1989-06-01), McAlpine

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