Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-06-18
2002-09-17
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S124000, C711S154000
Reexamination Certificate
active
06453391
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a multiplexed computer system, and more particularly to a multiplexed computer system in which memory copying for putting memories of the multiplexed computer system into coincidence with each other is effected.
BACKGROUND OF THE INVENTION
A conventional multiplexed computer system wherein a plurality of processing units execute a same calculation in synchronism with each other requires means for putting stored contents of memories of all of the processing units into coincidence with each other in order to allow the processing units to perform a same operation in synchronism with each other, that is, to perform a multiplexed operation again after one of the processing units is disabled because of a failure or a periodic inspection is performed for a particular one of the processing units.
As a method of putting stored contents of memories of all processing units which operate, for example, in a duplicated condition into coincidence with each other, the following two memory copying methods are adopted usually.
In particular, as the first memory copying method, in a computer system which operates in a duplicated condition, an operation of copying a fixed region of stored contents of a memory provided in one of processing units which is operating (hereinafter referred to as normal system processing unit) into another memory provided in another one of the processing units which is not operating (hereinafter referred to as abnormal system processing unit) using data transfer means of the normal system processing unit between a memory and a peripheral equipment, that is, so-called DMA engine, is repetitively executed after each fixed interval of time. Further, where a processor provided in the normal system processing unit is constructed so that it can access only the memory in the same processing unit, data to be written from the processor provided in the normal system processing unit into the memory of the same processing unit are transferred to the memory provided in the abnormal system processing unit. An example which discloses a technique regarding this is Japanese Patent Laid-Open Application No. Hei 3-182958.
As the second memory copying method, in a computer system which includes processing units which operate in a triplicated condition and global memories which operate in a duplicated condition and wherein each of the processing units includes a local memory and data transfer means between the local memory and the global memories, that is, so-called DMA engine, an operation of copying a fixed region of stored contents of one of the global memories which is operating (normal system) into the other global memory which is not operating (abnormal system) via the local memory provided in the processing unit using the DMA engine provided in the processing unit is repetitively executed after each fixed interval of time until all regions of the memory are copied. It is to be noted that, while the stored contents of the memory are being transferred, accessing to the global memories by a peripheral equipment, that is, DMA, is inhibited. A technique regarding this is disclosed in Doug Jewett, “Integrity S2: A Fault-Tolerant Unix Platform”, Twenty-First FTCS International symposium, Montreal, 1991.
A multiplexed computer system having an obstacle resisting function has a so-called on-line maintenance function of allowing repair or exchange a failed element while executing ordinary processing in order to allow a multiplexed operation to be performed again, and even while such on-line maintenance is performed, it is required to prevent deterioration of a processing performance. Accordingly, memory copying essentially required for on-line maintenance must be performed without making an obstacle to ordinary processing.
However, in memory copying in on-line maintenance, stored contents of the memory provided in the normal system processing unit which always vary by ordinary processing must be transferred to the memory provided in the abnormal system processing unit while maintaining the consistency, and the following problems which disturb this must be solved.
In particular, if the normal system processing unit reads out, immediately before certain regions of the memories provided in the normal system processing unit and the abnormal system processing unit are rewritten simultaneously by ordinary processing, the region of the memory thereof and transfers the thus read out data to the region of the memory of the abnormal system processing unit in order to perform memory copying, then after the regions of the memories of the normal system processing unit and the abnormal system processing unit are rewritten by ordinary processing, the data prior to such rewriting are copied into the region of the memory of the abnormal system processing unit. Consequently, the consistency between the memories of the normal system processing unit and the abnormal system processing unit is lost.
According to the first conventional method described above, memory coping is executed using the DMA engine provided in the normal system processing unit, and consequently, during execution of memory copying, DMA between the two system memories and a peripheral equipment by the DMA engine is not executed. Accordingly, during execution of memory copying, both of the memories are not rewritten by DMA, thereby solving the problem of the loss of the memory consistency described above.
Meanwhile, according to the second conventional system described above, memory copying is executed using a DMA engine provided in a processing unit, and consequently, during execution of memory copying, DMA between a local memory and the two system global memories by the DMA engine is not executed. Further, since DMA between a peripheral equipment and the two system global memories is inhibited during execution of memory copying, the two global memories are not rewritten by DMA during execution of memory copying, thereby solving the problem of the loss of the memory consistency described above.
However, those conventional methods have a problem in that, during execution of memory copying, DMA between a peripheral equipment and a memory and DMA between a local memory and a global memory cannot be executed. Further, they have another problem in that, since an operation of copying a fixed memory region by means of a DMA engine is executed repetitively after each fixed interval of time until all regions of the memory are copied, overheads by pre-processing for memory copying such as setting of a DMA engine or flushing of a cache memory are increased. It is to be noted that, since flushing of a cache memory is performed such that a region of the cache memory corresponding to a memory region to be copied is flushed before memory copying is executed and then, after copying of all of the memory regions is completed, the all regions of the cache memory are flushed again, cache flushing executed in memory copying is equal to the sum total of the memory capacity and the cache capacity. Those problems make causes of deterioration of the processing performance during on-line maintenance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory copying method for a multiplexed computer system composed of a plurality of processing units which allows memory accessing by a processor or a peripheral equipment even during execution of memory copying and minimizes overheads by pre-processing for memory copying.
In order to attain the object described above, there is provided a multiplexed computer system which includes a plurality of processing units which effect a same operation in synchronism with each other, and one or a plurality of peripheral equipments capable of accessing all of the processing units and wherein each of the processing units at least includes a processor or processors which effect operation processing, a cache and a memory unit which is accessible by the processor or processors and the peripheral equipment or equipments and the plurality of processing units are co
Kokura Shin
Miyazaki Naoto
Miyazaki Yoshihiro
Morita Yuuichiro
Nakamikawa Tetsuaki
Hitachi , Ltd.
Kenyon & Kenyon
Thai Tuan V.
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