Multiple word width memory array clocking scheme for reading wor

Static information storage and retrieval – Read/write circuit – Parallel read/write

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36518912, 365194, 365236, 365239, G11C 700

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active

058286179

ABSTRACT:
The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.

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Roland T. Knaack et al., U.S.S.N. 08/621,487 Memory Array Clocking Scheme to Write and Read Different Word Widths, Filed Mar. 25, 1996.
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