Multiple word-line accessing and accessor

Details Multiple word-line accessing and accessor Multiple word-line accessing and accessor

2001-08-28

2003-05-20

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S149000

Reexamination Certificate

active

06567329

ABSTRACT:

FIELD OF INVENTION
The present invention is in the field of memory device architecture. More particularly, the present invention provides a method, apparatus, system, and machine-readable medium to use a set of word-lines to access a row of memory cells.
BACKGROUND
A modern dynamic random access memory (DRAM) memory cell or memory bit comprises one transistor and one capacitor. The transistor operates as a switch between the capacitor and the bit-line and can be activated or deactivated by a word-line coupled to the base of the transistor. The memory cell can store binary information as a charge on the capacitor and the charge can be sensed by a sense amplifier comparing a bit-line acting as a signal bit-line and a bit-line acting as a reference bit-line. The binary information may be represented by positive or negative (V
D
-V
SS
)/2 volts across the capacitor to combine with a pre-charge on a bit-line of positive (V
D
-V
SS
)/2, where V
D
is a high voltage representing one binary bit and V
SS
is a low voltage representing a second binary bit.
Based on the spatial location of reference bit-lines to signal bit-lines, DRAM array organizations may be divided into at least two architectures: folded bit-line and open bit-line. Both the folded bit-line architecture and the open bit-line architecture have advantages and disadvantages. The folded bit-line architecture may comprise memory cells on a given word-line, coupled to every other bit-line so signal bit-lines are coupled a memory cell and are separated from other signal bit-lines by reference bit-lines. An advantage of this architecture is that it places the signal bit-line and reference bit-line in close proximity for good matching at the expense of a larger, less spatially efficient array layout. Consequently, the folded bit-line architecture has a low signal bit-line coupling, resulting in a low signal to noise ratio and the sense amplifiers can be pitched every four bit-lines, or quarter pitched, when alternate sense amplifiers are placed on either side of a memory bank. A disadvantage, however, is that separating active bit-lines by reference bit-lines can cause the coupling capacitance between adjacent bit-lines to be a large fraction of overall capacitance of a bit-line. In particular, when the signal bit-lines on either side of a reference bit-line read one or zero, the voltage on the reference bit-line moves in a like direction and the voltage differential between a signal bit-line and the reference bit-line may be reduced. A reduced voltage differential may increase read cycle (RC) delay.
In contrast to the folded bit-line architecture, the open bit-line architecture comprises spatially separated signal and reference bit-lines, facilitating a more compact cell. Since the bit-lines are adjacent, however, bit-line noise from capacitive coupling may be high and bit-line to word-line noise from capacitive coupling may contribute to the overall noise, particularly when the bit-line is operating as a signal bit-line during amplification and write-back. More importantly, during the write-back phase, when placing the charge back on the memory cell, the sense amplifier, driving a full swing signal into the cell, may cause the adjacent signal bit-line and reference bit-line to swing in opposite directions. For example, when all signal bit-lines read out zero, the reference bit-lines will be driven high during the write-back phase. Then, the reference bit-lines can induce a voltage on the word-lines of non-selected memory banks, causing the non-selected memory cells in the non-selected memory banks to be weakly activated. Activating non-selected memory cells can drain charge and the extent of the drainage may depend upon the severity of the coupling.


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Intel, PC SDRAM Specification, Revision 1.7, Nov. 1999. pp. 66.

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