Multiple twin cell non-volatile memory array and logic block...

Details Multiple twin cell non-volatile memory array and logic block... Multiple twin cell non-volatile memory array and logic block...

2007-02-13

2007-02-13

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185110, C365S185210

Reexamination Certificate

active

10675212

ABSTRACT:
Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.

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