Multiple transistor dynamic random access memory array architect

Details Multiple transistor dynamic random access memory array architect Multiple transistor dynamic random access memory array architect

1997-05-15

1999-03-09

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

365154, 365156, 36518908, 365203, G11C 700, G11C 1100, G11C 1604

Patent

active

058810102

ABSTRACT:
A four transistor dynamic memory cell architecture and refresh technique which allows for cell refresh to occur during a read operation. The access and memory transistors of the individual memory cells are fabricated with a relative width-to-length ratio such that it is sufficient to merely activate the associated word line to perform the refresh operation. This is accomplished without activating the read sense amplifier resulting in lower power consumption and the retention of most recently read data. Multiple word lines may be activated concurrently utilizing the technique disclosed to further reduce the refresh rate overhead in a memory array and increase the overall memory array bandwidth.

REFERENCES:
patent: 3893087 (1975-07-01), Baker
patent: 5020028 (1991-05-01), Wanlass
patent: 5446689 (1995-08-01), Yasui et al.
patent: 5706226 (1998-01-01), Chan et al.

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