Multiple transaction bus system

Details Multiple transaction bus system Multiple transaction bus system

2001-08-17

2004-08-10

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S313000

Reexamination Certificate

active

06775732

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is data transfer and data bus systems within computer systems.
BACKGROUND OF THE INVENTION
As computer systems have grown more complex, it has become common to employ multiple processors and a wide variety of peripheral devices to transfer data within a chip and from the chip to external devices and vice versa. Such systems almost always have a multiple set of busses separating, for convenience and performance reasons, the communication between similar devices. Multiple bus systems must provide bus controllers to allow for coherent and collision-free communication between separate buses. Micro-controllers are used for this purpose and they provide bus arbitration which determines, at a given time, which device has control of the bus in question.
A prominent standard bus system has emerged for high performance micro-controller designs. The ‘Advanced Micro-controller Bus Architecture System’ AMBA has been defined by Advanced RISC Machines (ARM) Ltd. (Cambridge, U.K.) and is described in U.S. Pat. No. 5,740,461, dated Apr. 14, 1998. Computer systems of a CISC variety are complex instruction set computers and have total backward compatibility requirements over all versions. RISC (reduced instruction set computer) systems, by contrast, are designed to have simple instruction sets and maximized efficiency of operation. Complex operations are accomplished in RISC machines as well, but they are achieved by using combinations of simple instructions. The RISC machines of ARM Ltd. forming the AMBA architecture are of primary interest here.
The standard AMBA has two main busses, a high performance AHB bus and a peripheral bus APB of more moderate performance. The AHB bus is the main memory bus and contains RAM and an external memory controller. In this basic system definition, if a high performance peripheral is required that will transfer large amounts of data, this peripheral is also placed on the high performance AHB bus. This decreases system performance, however, because the central processor unit (CPU) cannot have access to memory when the peripheral has control of the bus.
Advanced RISC Machines Ltd (ARM) has proposed an efficient arbitration scheme and split transfers to allow the CPU and the high performance peripheral to share bus time of the single AHB bus. ARM has also proposed use of a second bus for isolation and using a single arbiter. This proposal still allows only one transaction to progress at a given time period.
SUMMARY OF THE INVENTION
This invention comprises a multiple transaction advanced high performance bus (MTAHB) system using two separate fully autonomous AHB-style buses. Each of these buses has its own bus arbitration system with decoding to allow for simultaneous activity on the two AHB-style buses. The first bus, the high performance memory bus, is exactly as defined for AHB busses in the AMBA specification of ARM. This AHB bus contains the CPU and direct memory access (DMA) unit as bus masters and the external memory interface controller and internal memory as bus slaves. The second bus, the high performance peripheral device bus (HTB), is also exactly as defined for AHB busses in the AMBA specification of ARM. The HTB contains the high performance peripheral and any local RAM required. The two buses are separated by and synchronized with an AHB-to-HTB bus bridge.
The extended AMBA system of this invention is referred to as the multiple transaction advanced high performance bus system (MTAHB) and it allows the CPU and the high performance peripheral to accomplish bus activity simultaneously. This is achieved by these devices residing on two separate AHB buses with individual, autonomous arbitration. System performance is increased because, instead of having just one bus master (either the CPU, the DMA or the high performance peripheral device) use the single AHB bus at any given time, two bus masters may perform work in the system concurrently. In this scheme both the memory bus master of the AHB bus and the high performance peripheral device master of the HTB bus have control of their individual AHB-style busses and can do work concurrently.


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