Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1998-12-07
2004-05-11
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
Reexamination Certificate
active
06734925
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to liquid crystal displays (referred as LCDs hereinafter), manufacturing methods thereof and testing methods thereof, in particular, to LCDs having more than two shorting bars, and methods for detecting defects in the LCDs by using the shorting bars.
(b) Description of the Related Art
Shorting bars of a liquid crystal display are used to discharge a electrostatic charges generated in the manufacturing process of the LCD and to test the LCD after the manufacturing process is completed.
A conventional LCD is described in detail with reference to the accompanying drawings.
FIG. 1
is a schematic diagram of a conventional thin film transistor (referred as TFT hereinafter) substrate for an LCD having shorting bars,
FIG. 2
is an enlarged view of the part A in FIG.
1
and
FIG. 3
is a cross-sectional view taken along line III-III′ in FIG.
2
.
As shown in
FIGS. 1
to
3
, gate lines G
1
, G
2
, G
3
, G
4
, . . . are formed on a substrate
1
and extend in the horizontal direction, and a gate pad
10
is formed at one end of each gate line. A gate shorting bar
20
that electrically connects the gate lines G
1
, G
2
, G
3
, G
4
, . . . all together and is formed on the substrate
1
, extends in the vertical direction, and is located opposite the gate lines G
1
, G
2
, G
3
, G
4
, . . . with respect to the gate pads
10
. A pair of testing pads
2
are formed at both ends of the gate shorting bars
20
.
A gate insulating film
15
covers a gate wire
5
such as the gate lines G
1
, G
2
, G
3
, G
4
, . . . , the gate pads
10
and the gate shorting bar
20
. Data lines D
1
, D
2
, D
3
, D
4
, . . . are formed on the gate insulating film
15
and extends in the vertical direction, and a data pad
30
is formed at one end of each data line. A data shorting bar
40
that electrically connects the data lines D
1
, D
2
, D
3
, D
4
, . . . all together is formed on the gate insulating film
15
, extends in the horizontal direction. A pair of testing pads
3
are formed at both ends of the date shorting bars
40
. The gate shorting bar
20
and the data shorting bar
40
may be connected to each other by a resistor.
An insulating film
25
covers a data wire including the data lines D
1
, D
2
, D
3
, D
4
, . . . , the data pads
30
and the data shorting bar
40
, and some portions of the insulation films
15
and
25
on the data pads
30
and the gate pads
10
are removed.
Pixel regions are defined as the area surrounded by the two adjacent gate lines and the two adjacent data lines, and a display area includes the pixel regions. A TFT that turns on by a scan signal from the gate line and transmits image signals from the data line into the pixel region is formed in each of the pixel regions.
In this structure, electrostatic charges generated in the manufacturing process are discharged or dispersed through the gate shorting bar
20
and the data shorting bar
40
.
Meanwhile, after the manufacturing process and the array test are finished, the gate shorting bar
20
and the data shorting bar
40
are removed by cutting the substrate along line L.
Next, the mechanism of a conventional array test is described with reference to
FIGS. 1 and 4
.
FIG. 4
shows polarities of signals for an array test that are applied to the pixel regions.
Voltages for an array test are applied to the testing pads
2
and
3
. Since the gate lines G
1
, G
2
, G
3
, G
4
, . . . and the data lines D
1
, D
2
, D
3
, D
4
, . . . are respectively connected to the shorting bars
20
and
40
, the TFTs of the pixel regions turn on simultaneously and a testing signal is applied in all R, G, B pixels as shown in FIG.
4
. Therefore, in the normally white mode, the pixel regions PX represent dark state.
In case either that the wires are disconnected or that the TFT has a defect, the pixels related to the defects turns to a bright states, and thus the defected elements may be detected with ease. However, if more than two gate lines or data lines, for example, the data lines D
2
and D
3
in
FIG. 1
, are short-circuited (S
1
), it is hard to detect the short-circuited elements since the voltage of the same magnitude and polarity is applied to the two data lines D
2
and D
3
.
Meanwhile, if the shorting bar become divided into more than two and connected different gate lines or data lines to solve the previously described disadvantage, the detecting capability may increase. However, the protecting capability against electrostatic charges may decrease.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a TFT array panel having shorting bars that are superior in detecting short-circuit defects as well as discharging electrostatic charges.
It is another object of the present invention to provide a test methods to detect short-circuit defects between adjacent data lines or adjacent gate lines and pixel defects with ease.
It is another object of the present invention to provide a test method to effectively detect some defects in a high-resolution substrate.
To achieve these objects of the present invention, a plurality of gate lines are formed in parallel with one another and two shorting bars for tests are formed in a manner to respectively link every other gate lines. A main shorting bar linking all gate lines is formed outside the shorting bars.
The gate lines and the shorting bars for test may be coupled by conductive coupling patterns.
A plurality of data lines may be formed in perpendicular to the gate lines, three shorting bars for tests may respectively link to the sequences of the data lines one after another and the data shorting bars and the data lines may be coupled to each other by conductive coupling patterns.
Moreover, it is desirable that the gate lines and the data lines link all together outside the data shorting bars by the main shorting bar.
In a method of manufacturing the LCD, the conductive coupling patterns are formed at the step of forming transparent pixel electrodes.
The gate lines and the data lines may be separated from the main shorting bar after the conductive coupling patterns are formed.
According to the LCDs and the manufacturing methods of the present invention, the additional gate shorting bars or the additional data shorting bars are formed and separated from the main shorting bar after the process is over. Accordingly, the LCD substrate is superior in detecting short-circuited defects of the substrate as well as in discharging the electrostatic charges.
In testing methods according to embodiments of the present invention, gate pulses are applied to two secondary lines for tests that are respectively connected to even gate lines and to odd gate lines and data signals are applied to three secondary lines for test that are respectively connected to one of R, G and B pixels in sequence. In detail, a signal having the first polarity is applied to two of three adjacent data lines and a signal having the opposite polarity of the first is applied to the rest of the three adjacent data lines when the pulse is applied to the even gate lines. Then, the signal having the first polarity is applied to two of the three adjacent data lines chosen in a different combination concerning to the first choice and the signal having the opposite polarity of the first is applied to the rest of the three adjacent data lines.
In this test method according to the present invention, it is possible to detect short-circuited defects between adjacent pixels or adjacent wires, and the detecting ability of visual defects and the reliability are increased.
REFERENCES:
patent: 5598283 (1997-01-01), Fujii et al.
patent: 5668032 (1997-09-01), Holmberg et al.
patent: 6005647 (1999-12-01), Lim
patent: 6013923 (2000-01-01), Huang
patent: 6025891 (2000-02-01), Kim
patent: 6111620 (2000-08-01), Nishiki et al.
patent: 2001/0045997 (2001-11-01), Kim
Kim Dong-Gyu
Lee Sang-Kyoung
Moon Min-Hyung
McGuireWoods LLP
Parker Kenneth
Samsung Electronics Co,. Ltd.
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