Multiple substrate bias random access memory device

Details Multiple substrate bias random access memory device Multiple substrate bias random access memory device

1997-08-12

1999-04-13

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257369, H01L 27108

Patent

active

058941452

ABSTRACT:
A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

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Syuso Fujii, et al., A 45ns 16Mb DRAM with Triple-Well Structure, 1989 IEEE International Solid-State Circuits Conference, pp. 248-249, Feb. 1989.

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