Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-11-22
2002-10-08
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S724000, C252S079100
Reexamination Certificate
active
06461969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of manufacture of microelectronics fabrications. More particularly, the invention relates to the field of etching of microelectronics layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are manufactured employing layers of microelectronics materials formed sequentially on substrates. Microelectronics conductor layers, often patterned into lines and shapes, are insulated from each other and other conductor regions by microelectronics dielectric layers. In the fabrication of particular geometries of microelectronics materials, it is necessary to form patterns from layers of such materials. This is commonly done employing subtractive etching of the microelectronics material layer through patterned etch mask resist layers formed upon the microelectronics layer. In other cases, the patterned mask layer acts as a barrier layer to avoid a particular reaction of a layer.
Among the microelectronics materials employed in microelectronics fabrication, silicon nitride is widely used both for its dielectric properties and for its etch resistant properties. In order to etch patterns in silicon nitride layers conveniently, it is common practice to employ dry etch methods involving plasma activation of reactive ions. In order to obtain high resolution patterned layers of silicon nitride with variable spacing and maintain control over the profiles of high aspect ratio pattern features, the etching processes often employ multiple process steps and materials for optimum performance. The selectivity of the etching of silicon nitride layers compared to other materials is important, since silicon nitride layers are often formed over other materials, in which case it is often necessary to assure the etching of the silicon nitride layer completely while keeping the underlying layer essentially unaffected and intact.
There is a need for selectively etching of a patterned silicon nitride layer to maintain critical dimensional control of the silicon nitride layer pattern under conditions of variable microloading of the substrate being etched while avoiding significant damage to underlying material layers. While satisfactory methods for plasma etching of silicon nitride layers in general are available, such methods are not without difficulties. For example, the etching of a high aspect ratio feature within a silicon nitride layer may result in trench formation through the silicon nitride at the foot of the feature while the region away from the foot may still contain unetched silicon nitride material. In addition, the selectivity of the silicon nitride etch rate ratio may not be very high compared to other adjacent or underlying materials.
Various methods have been disclosed for etching patterns within silicon nitride dielectric layers formed upon other materials in dry plasma etch environments with various rate selectivity.
For example, Long, in U.S. Pat. No. 5,013,398, discloses a method for etching a sandwich structure of silicon oxide/silicon/silicon oxide dielectric layers in a single chamber. The method employs sulfur hexafluoride and trifluoromethane to etch silicon oxide, and hydrogen bromide to etch silicon. Silicon nitride may be used in place of silicon oxide.
Further, Cheung et al., in U.S. Pat. No. 5,354,417, disclose a method for selective etching of a molybdenum silicide layer through a resist mask. The method employs sulfur hexafluoride and hydrogen bromide gases, with oxygen preferably added to the gas mixture.
Still further, Huang et al., in U.S. Pat. No. 5,854,136, disclose a multi-step method for etching a layer of silicon nitride over a layer of silicon oxide. The three-step method employs a first anisotropic etching environment of CHF
3
, SF
6
and He gases to etch the bulk of the silicon nitride layer, followed by a second step in which HBr replaces CHF
3
to etch the remainder of the silicon nitride and provide a small amount of over-etching. A third step employs addition of an oxidizing gas to the etching mixture to assure removal of residues.
Finally, Padmapani et al., in U.S. Pat. No. 5,877,090, disclose a method for etching a silicon nitride dielectric layer over a silicon oxide dielectric layer. A plasma sustaining gas that includes nitrogen is employed with hydrogen bromide and one or both of nitrogen trifluoride and sulfur hexafluoride.
Desirable in the art of microelectronics fabrication are additional methods for etching patterns with high aspect ratios in silicon nitride dielectric layers employing dry plasma etch methods with varying selectivity of etching rates.
It is towards these goals that the present invention is generally directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for dry plasma selective etching of a pattern in a silicon nitride dielectric layer formed over a substrate employed within a microelectronics fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where there is selectively etched a pattern in a silicon nitride layer employing dry plasma environments with critical dimensional control and attenuated microloading and etching of underlying layers.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, where the invention is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for selective dry plasma etching of patterns in silicon nitride dielectric layers. To practice the invention, there is provided a silicon substrate having formed thereupon a silicon oxide pad oxide layer over which is formed a silicon nitride dielectric layer. There is formed over the substrate a patterned photoresist etch mask layer. There is then selectively etched the pattern of the photoresist etch mask into the silicon nitride layer employing a four-step dry plasma etching process in three plasma etching environments which include: (1) a first “break-through” etching step to initiate pattern formation; (2) a second “bulk” etching step of the major portion of the silicon nitride layer and a third “buffer” etching step to complete the patterned silicon nitride layer; and (3) a fourth “over-etch” etching step to assure complete removal of silicon nitride without excessive etching of underlying layer. These steps comprise the selective etching of silicon nitride pattern with critical dimensional control whereby there is attenuated microloading effects and the excessive etching of underlying material.
The method of the present invention may be practiced on silicon nitride dielectric layers formed over silicon substrates employed within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications, charge coupled display microelectronics fabrications, solar cell microelectronics fabrications and optoelectronics display microelectronics fabrications.
The present invention employs materials and methods which are known in the art of microelectronics fabrication but in a novel order and sequence. Therefore the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 4816115 (1989-03-01), Horner et al.
patent: 5013398 (1991-05-01), Long et al.
patent: 5354417 (1994-10-01), Cheung et al.
patent: 5644153 (1997-07-01), Keller
patent: 5854136 (1998-12-01), Huang et al.
patent: 5877090 (1999-03-01), Padmapani et al.
patent: 6121154 (2000-09-01), Haselden et al.
Jimenez, A. J., Recessed Oxide Isolation Having a Planar Surface, IBM Technical Disclosure Bulletin, vol. 26, No. 9, pp 4787 and 4788, Feb. 1984.
Lee Pei Ching
Liu Wen Jun
Zhou Mei Sheng
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Stanton Stephen G.
Umez-Eronini Lynette T.
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