Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2001-04-12
2002-12-03
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S112000, C327S318000
Reexamination Certificate
active
06489829
ABSTRACT:
BACKGROUND
Many applications deliver power to electrical systems, or loads, through power MOSFET switches. Often, a single power source drives several loads, each with its own power MOSFET switch. If one power MOSFET is switched on quickly, the change in voltage combined with the typically low on-resistance of the power MOSFET can cause a large current surge, called a “rush current,” to flow through the power MOSFET to the load. The rush current can cause voltage fluctuations and possibly trigger malfunction of the load circuits. In particular, fluctuations in the power source voltage can cause other load circuits to turn off in response to under-voltage lock-out protection schemes. Thus, minimizing the rush current is important for reliable operation of the load circuits.
Most prior art designs focus on incorporating protection circuits in the loads to handle the rush current generated during switching. It is more efficient and more desirable, however, to reduce the generated rush current and prevent a high current from reaching the loads at all. One way to minimize the rush current, is to gradually increase the power delivery capability of the power MOSFET switch over a finite turn-on time.
FIG. 1
a
is a circuit diagram of a prior art circuit
100
to control power MOSFET rush current. A p-type power MOSFET
105
has a drain labeled VOUT, a source labeled VIN, a gate
130
, and a body. As is common in power MOSFETs, the source and body are shorted together to prevent the parasitic bipolar junction transistor inherent in power MOSFET
105
from turning on. A first resistor
115
is coupled between gate
130
and the source of power MOSFET
105
. A capacitor
125
is coupled between gate
130
and the drain of power MOSFET
105
. The drain of an n-type control MOSFET
110
is coupled to gate
130
of power MOSFET
105
. A control signal is applied to a gate, labeled ON/OFF, of control MOSFET
110
. A second resistor
120
is coupled between the source of control MOSFET
110
and ground, labeled GND. In circuit
100
, a power source (not shown) is applied at VIN, and a load (not shown) is driven by VOUT.
When the control signal is ON, a “high” voltage, for example 5V, is applied to the gate of control MOSFET
110
, thereby turning control MOSFET
110
on and allowing it to conduct current. When the control signal is OFF, a “low” voltage, for example 0V, is applied to the gate of control MOSFET
110
, thereby turning control MOSFET
110
off and prohibiting it from conducting current.
In the off state of power MOSFET
105
, the control signal applied at the gate of control MOSFET
110
is low (OFF), and control MOSFET
110
is off. Since no current flows through control MOSFET
110
, the voltage at gate
130
of power MOSFET
105
is equal to VIN, the power source voltage, which may be, for example, 5V. The voltage across capacitor
125
is |VIN−VOUT|.
When the control signal at the gate of control MOSFET
110
is turned ON (high), control MOSFET
110
turns on and begins to conduct current. Current flows along the path from VIN through resistor
115
, through control MOSFET
110
, and through resistor
120
to GND. The voltage on gate
130
of power MOSFET
105
begins to decrease slowly since it is limited by charging of capacitor
125
.
FIG. 1
b
is a gate voltage vs. time plot for power MOSFET
105
of prior art circuit
100
of
FIG. 1
a.
The plot shows a gate voltage curve
150
at gate
130
of power MOSFET
105
during a finite turn-on time, for example, 1.6 ms. At t=0 ms, the voltage at gate
130
is VIN, i.e. 5V. As shown in the plot, the voltage at gate
130
of power MOSFET
105
decreases slowly in an initial stage
152
.
Power MOSFET
105
begins to turn on when the gate
130
to source (VIN) voltage drops below the threshold voltage of power MOSFET
105
. For example, if the threshold voltage of power MOSFET
105
is V
T
=−1V, power MOSFET
105
begins toturn when the voltage at gate
130
reaches 4V for VIN=5V which is shortly before t=0.2 ms in
FIG. 1
b.
Initial stage
152
of the voltage decrease at gate
130
is a “dead time” in the finite turn-on time since power MOSFET
105
is not conducting.
The voltage on gate
130
of power MOSFET
105
continues to decrease through a middle stage
154
as shown in
FIG. 1
b.
During this time, the on-resistance of power MOSFET
105
decreases nonlinearly. When the gate
130
to source (VIN) voltage reaches twice the threshold voltage of power MOSFET
105
, power MOSFET
105
is essentially fully on. This occurs, for example, when the voltage at gate
130
reaches 3V, for VIN=5V and V
T
=−1V, which is near t=0.6 ms in
FIG. 1
b.
After this point, the voltage at gate
130
decreases through a final stage
156
, as shown in
FIG. 1
b,
until the maximum drive on power MOSFET
105
is reached when the voltage at gate
130
is approximately 0V at the end of the finite turn-on time at t=1.6 ms. This is accomplished by having the resistance of resistor
115
be much larger than the resistance of resistor
120
. The time to reach maximum drive is approximately t=1 ms in this example. During this time, the on resistance of power MOSFET
105
changes very little and is non-linear. Thus, the load driven by VOUT is supplied with the power source voltage VIN.
FIG. 1
c
is a current vs. time plot showing the current through power MOSFET
105
of prior art circuit
100
of
FIG. 1
a.
A current curve
180
has two notable features. A rush current
182
flows which is much higher than the level of a final current
186
. Rush current
182
supplies the initial current to charge capacitor
125
.
When the control signal at the gate of control MOSFET
110
is turned OFF (low), control MOSFET
110
stops conducting current. The voltage at gate
130
of power MOSFET
105
discharges through resistor
115
and capacitor
125
.
The goal of prior art circuit
100
is to apply a constant force to gate
130
of power MOSFET
105
in order to control the rush current. Prior art circuit
100
, however, has several disadvantages. First, circuit
100
has a fairly large dead time before power MOSFET
105
turns on and begins conducting. Second, circuit
100
requires a fairly large time to reach maximum drive (i.e. when the voltage on gate
130
reaches 0V) after power MOSFET
105
turns on. Third, when control MOSFET
110
is turned on, circuit
100
conducts a large quiescent current thus dissipating high power. Fourth, when control MOSFET
110
is turned off, circuit
100
requires a long time before the voltage at gate
130
rises again to VIN.
The slow rates of change of the voltage on gate
130
to one threshold and then to maximum drive are undesirable, since they do not provide optimal rush current control. Prior art circuits using this constant driving force technique must compromise between turn-on time and driving force, resulting in non-optimal rush current control.
Thus, there is a clear need for a circuit that can optimize the drive force applied to the gate of a power MOSFET switch to minimize rush current delivered to a load through the power MOSFET.
SUMMARY
The present invention describes circuits and methods to limit rush current delivered from a power source to a load though a power MOSFET switch. The power MOSFET may be either a p-type power MOSFET or an n-type power MOSFET. In an exemplary circuit arrangement, the power source has a power terminal and a ground terminal. A first terminal of the power MOSFET is coupled to one of the power source terminals. The load is coupled to a second terminal of the power MOSFET.
The circuit arrangement also includes a control circuit including at least three inputs, the first of which is an enable signal, and at least three outputs. The control circuit is adapted to control the drive force applied to the power MOSFET gate, based on the inputs to the control circuit, to control the turn-on of the power MOSFET and to limit the rush current through the power MOSFET.
The circuit arrangement also in
Advanced Analogic Technologies, Inc.
Cunningham Terry D.
Silicon Valley Patent & Group LLP
Steuber David E.
Tra Quan
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