Multiple stacked-chip packaging structure

Details Multiple stacked-chip packaging structure Multiple stacked-chip packaging structure

2001-06-28

2003-04-29

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S685000, C257S777000, C257S723000, C257S787000, C257S773000

Reexamination Certificate

active

06555902

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89114232, filed Jul. 17, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor packaging structure, and more particularly to a semiconductor BGA packaging structure.
2. Description of the Related Art
As the era of information technology progresses, integrated circuits are present in every aspect of daily life. As semiconductor technology progresses, the design tends to lighter, thinner, shorter and smaller products in order to provide customers with comfortable use.
Semiconductor manufacturing has already entered the level of 0.18-micron, and semiconductor products having better performance are forthcoming. The manufacturing of IC products is essentially composed of 3 principal stages: semiconductor wafer production, IC manufacturing, and IC packaging. Packaging is thus the last stage in the manufacturing of the IC product. The purpose of packaging is to protect the chip and to connect electrically the chip to a printed circuit board or other adaptable carrier elements. The chip then can be connected to an external device through the carrier element.
Issues related to the conventional packaging structures are now described with the help of
FIG. 1
, FIG.
2
and FIG.
3
.
FIG. 1
schematically shows a cross-sectional view of a conventional stacked-chip packaging structure. Generally, Ball Grid Array structure is employed in combination with a chip stacking structure, like the stacking of memory chips, to increase the capacity of the packaged product. As shown in
FIG. 1
, a first semiconductor chip
106
is mounted on a substrate
102
, a second semiconductor chip
108
is mounted on the first semiconductor chip
106
. The substrate
102
, the first semiconductor chip
106
and the second semiconductor chip
108
are respectively fixed to one another with an adhesive layer
104
. In the following wire bonding process, the first semiconductor chip
106
and the second semiconductor chip
108
are electrically connected to the substrate
102
respectively through wires
110
a
and
110
b.
The substrate
102
, the first semiconductor chip
106
, the second semiconductor chip
108
, and the wires
110
a
and
110
b,
are encapsulated by a molding compound
114
. Finally, solder balls
112
are attached to the substrate
102
to complete the BGA structure. In the foregoing conventional packaging structure, a necessary condition is that the dimensions of the first semiconductor chip
106
have to be greater than the dimensions of the second semiconductor chip
108
. For example, the difference between the length of the first semiconductor chip
106
and the length of the second semiconductor chip
108
must be at least 0.3 mm. Otherwise the wire bonding would be difficult to achieve, and the second semiconductor chip
108
may be short-circuited by touching the wire
110
a.
FIG.
2
A and
FIG. 2B
are respectively top and cross-sectional views of another conventional packaging structure wherein various semiconductor chips are side-by-side arranged.
FIG. 2B
is the cross-sectional view of the structure taken along line
2
B—
2
B of FIG.
2
A.
As shown in FIG.
2
A and
FIG. 2B
, a principal semiconductor chip
205
and other secondary semiconductor chips
206
,
208
,
209
and
211
are arranged side-by-side on a substrate
202
. The principal semiconductor chip
205
, and the secondary semiconductor chips
206
,
208
,
209
and
211
are bonded to the substrate
202
via a plurality of adhesive layers
204
. All the semiconductor chips are electrically connected to the substrate
202
through wires
210
. A molding compound
214
encapsulates the substrate
202
, the semiconductor chips
205
,
206
,
208
,
209
,
211
, and the wires
210
. Solder balls
212
are attached to the substrate
202
to complete the conventional packaging structure. In such a conventional packaging structure, an advantage is that various semiconductor chips with different functionality can be integrated within a single packaging structure. However, a substantial drawback is that the semiconductor chips occupy a large surface of the substrate
202
. As a result, the routability of the substrate
202
becomes more complex, and necessitates the use of a high-density trace substrate. Moreover, the side-by-side arrangement of the semiconductor chips can also limit the number of semiconductor chips that may be arranged on the substrate, which consequently limits also the functions that may be integrated in a single package. The resulting functional enhancement can be thus substantially limited.
FIG. 3
is a cross-sectional view of another conventional stacking structure of a lead frame carrier disclosed in the U.S. Pat. No. 5,291,061 issued to Ball. In this conventional package, two semiconductor chips
306
and
308
have approximately the same size. The first semiconductor chip
306
is placed on the lead frame
302
and, through the wires
310
a
, is connected to the lead frame
302
. Via a polyimide tape
330
placed on the semiconductor chip
306
, the second semiconductor chip
308
is stacked on the first semiconductor chip
306
. Wires
310
b
connect the semiconductor chip
308
to the lead frame
302
. A molding compound
314
encapsulates the lead frame
302
, the semiconductor chips
306
and
308
, and the wires
310
a
and
310
b
, leaving the outer portion of the leads
332
of the lead frame carrier
302
externally exposed.
Various disadvantages are related to the packaging structure shown in
FIG. 3
, as discussed hereafter. The cost of the polyimide tape is high, and specific equipment is required to attach the semiconductor chips to the polyimide tape through a high temperature process above 400° C., which causes a high manufacturing cost. Moreover, vis-à-vis the top semiconductor chip, the polyimide tape may generate a “cushion effect” and affect the reliability of the wire bonding. The cushion effect is due to the insufficient rigidity of the semiconductor chips.
SUMMARY OF THE INVENTION
An aspect of the invention is to provide a multiple stacked-chip packaging structure, wherein a plurality of semiconductor chips are contiguously arranged into a plurality of stacked semiconductor chip levels. The multiple stacked-chip packaging structure of the invention prevents a cushion effect and maintains the dimensions of the packaging structure. Without necessitating any specific equipment, the manufacturing cost of the packaging structure of the invention is reduced.
To achieve at least the foregoing aspects of the invention, the multiple stacked-chips packaging structure of the invention comprises: a substrate, a plurality of semiconductor chips having respectively a plurality of bonding pads, a plurality of supporting members, a plurality of adhesive layers, a plurality of bonding wires and a molding compound. The substrate has a front surface and a back surface opposite to the front surface. The semiconductor chips are contiguously mounted into a plurality of semiconductor chip sets that are stacked upon the front surface of the substrate, wherein the size of two consecutive semiconductor chip sets at two adjacent levels of the stack is approximately equal to each other, or their difference does not exceed 0.3 mm. The supporting members are respectively mounted between two consecutive chip sets, while the adhesive layers bond the supporting members, the semiconductor chips, and the substrate to one another. In each semiconductor chip set of the stack structure, the semiconductor chips can be connected to one another or to the substrate. The molding compound encapsulates the front surface of the substrate, the supporting members, the semiconductor chip sets and the adhesive layers.
According to a preferred embodiment of the invention, the adhesive layers are made of silver paste or non-conductive paste such that the process does not require a high temperature, which simplifies the fabrication process and prevents chip c

Affiliated with

Also associated with

Rating

Multiple stacked-chip packaging structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple stacked-chip packaging structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple stacked-chip packaging structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3022130