Multiple signal format output buffer

Details Multiple signal format output buffer Multiple signal format output buffer

2006-12-05

2006-12-05

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S115000

Reexamination Certificate

active

07145359

ABSTRACT:
An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.

REFERENCES:
patent: 5121080 (1992-06-01), Scott, III et al.
patent: 5374861 (1994-12-01), Kubista
patent: 5402485 (1995-03-01), Takato et al.
patent: 5550496 (1996-08-01), Desroches
patent: 5570037 (1996-10-01), Llorens
patent: 6054881 (2000-04-01), Stoenner
patent: 6147520 (2000-11-01), Kothandaraman et al.
patent: 6280011 (2001-08-01), Schloeman et al.
patent: 6281702 (2001-08-01), Hui
patent: 6300802 (2001-10-01), Smetana
patent: 6433579 (2002-08-01), Wang et al.
patent: 6437599 (2002-08-01), Groen
patent: 6445223 (2002-09-01), Thilenius
patent: 6504397 (2003-01-01), Hart et al.
patent: 6580292 (2003-06-01), West et al.
patent: 6603329 (2003-08-01), Wang et al.
patent: 6664814 (2003-12-01), Evans et al.
patent: 6670830 (2003-12-01), Otsuka et al.
patent: 6700403 (2004-03-01), Dillon
patent: 6744275 (2004-06-01), Chansungsan
patent: 6812734 (2004-11-01), Shumarayev et al.
patent: 6815980 (2004-11-01), Kerr
patent: 6940302 (2005-09-01), Shumarayev et al.
patent: 6963219 (2005-11-01), Ghia et al.
patent: 2005/0212553 (2005-09-01), Best et al.
Goldie, John, “LVDS, CML, ECL-differential interfaces with odd voltages,” http://www.planetanalog.com/ Jan. 21, 2003, 9 pages.
Ju, Jeff, “Interfacing LVDS with other differential-I/O types,”www.edn.com, Oct. 30, 2003, 4 pages.
MAXIM High-Frequency/Fiber Communications Group, “Introduction to LVDS, PECL, and CML,” Application Note: HFAN-1.0, Rev. 0, Sep. 2000, pp. i-14.
Heydari, Payam, “Design Issues in Low-Voltage High-Speed Current-Mode Logic Buffers,”GLSVLSI'03, Apr. 28-29, 2003, Washington, DC, USA, 6 pages.
Boni, Andrea, et al., “LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-μm CMOS,”IEEE Journal of Solid-State Circuits, vol. 36, No. 4, Apr. 2001, pp. 706-711.
Chen, Mingdeng, et al., “Low-Voltage Low-Power LVDS Drivers,”IEEE Journal of Solid-State Circuits, vol. 40, No. 2, pp. 472-479, Feb. 2005.
Kumeric, Marijan, et al., “Digitally tuneable on-chip line termination resistor for 2.6Gbit/s LVDS receiver in 0.25μ standard CMOS technology,” inProceedings of the 27thEuropean Solid-State Circuits Conference(ESSCIRC 2001), Sep. 18-20, 2001, pp. 241-244.
“HiPerClockS (TM) Application Note, 3.3V LVPECL Driver Termination,” Integrated Circuit Systems, Inc., Aug. 2, 2002, 7 pages, retrieved from URL www.icst.com/products/hiperclocks.html.
Ma, Jimmy, “Termination Schemes and Design Guidelines for 3.3V LVPECL Driver,” Application Note #73, Pericom Semiconductor Corporation, San Jose, CA, May 19, 2004, 2 pages, retrieved from URL www.pericom.com.
Micrel Semiconductor, “High-Speed PECL and LVPECL Termination,” (no date) 2 pages, retrieved from URL www.micrel.com/solutions.shtml.
“Optimizing Design and Layout for the Si5318/20/21/64 Clock ICs,” Silicon Laboratories Product Sheet AN59, Rev. 1.0, Jun. 2005, 20 pages.
Von Herzen, Brian and Brunetti, Jon, “Virtex-E LVPECL Receivers in Multi-Drop Applications,” XILINX Application Note: Virtex-E Family, Feb. 24, 2000, 8 pages, XAPP237, v1.1, retrieved from URL www.xilinx.com.
Yang, Ken, “Modified LDO Regulator Sinks PECL-Termination Current,” Planet Analog, Jun. 28, 2005, 4 pages, retrieved Sep. 2, 2005 from URL http://www.planetanalog.com/showArticle?articleID=164903593.

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