Multiple segmenting of main memory to streamline data paths in a

Details Multiple segmenting of main memory to streamline data paths in a Multiple segmenting of main memory to streamline data paths in a

1997-04-23

1998-06-16

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711153, G06F 1300

Patent

active

057685479

ABSTRACT:
Within a computing system, the main memory is segmented in order to streamline data paths for data transactions between input/output devices. The computing system includes both a host bus and an input/output bus. One or more processors are connected to the host bus. A bus bridge connects the input/output bus to the host bus. The bus bridge is used for transferring information between the host bus and the input/output bus. The main memory for the computing system is segmented as follows. A first main memory segment is connected to the host bus. A second main memory segment is connected to the input/output bus. The first main memory segment and the second main memory segment are configured to appear to the processors as a single logical memory image. The segmented main memory is used to streamline data paths for the computing system. For example, a data transfer between a first input/output device and a second input/output device is controlled by the processor; however, during the first data transfer, the data itself is temporarily stored in the second main memory segment. This allows the data transfer to occur with only control information flowing through the bus bridge. The actual data is transported only on the input/output bus between the second main memory segment and the first input/output device, and between the second main memory segment and the second input/output device.

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