Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-03
2001-12-11
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000
Reexamination Certificate
active
06329278
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the packaging of semiconductor devices, and more particularly to wire bonding of semiconductor devices. Even more particularly, the present invention relates to wire bonding of bond pads, of a multiple row bond pad layout die, and leads, while minimizing loop height of wire loops formed therebetween, such that multiple row bond pad layout dies can be used in thin semiconductor packages.
In view of the increasing miniaturization of semiconductor devices and the packaging thereof, a dimension of concern to semiconductor package designers is not only the length and width of the package, but also the thickness of the final packaging. In many applications, such as cellular telephone technologies, it is desirable to have as thin a semiconductor package as possible due to the decreasing overall size of such devices. Advantageously, advances in packaging have resulted in the development of very thin packages, such as TQFPs (Thin Plastic Quad Flat Pack), MGBAs (Mini Ball Grid Array), and CSPs (Chip Scale Package), as known in the art.
Prior art wire bonding techniques for such thin packages form the wire interconnection between the bond pad of the chip or die and the leads (also referred to as “lead fingers”) of the lead frame, or leads of the substrate in ball grid array (EGA) packages, by forming a ball bond on the bond pads of the die and looping the wire up and over to the leads where stitch bonds are formed thus completing the wire interconnection. As the wires leave the ball bonds formed on the bond pads of the die, each wire forms a loop defining a loop height of the wire interconnect. The wire loop height is the height above the plane of the bond pad that is required for the wire to bend without damaging the wire. The normal loop height is generally about 0.010 to 0.015 inches in height which has accordingly resulted in a package thickness to accommodate this loop height. As thinner packages have been developed, the loop height has been reduced down to as small as 0.006 inches in height by changing loop parameters, profile, and wire types. This loop height is considered a minimum loop height, since a smaller loop height may cause damage or cracking to the wire. Thus, the loop height directly effects the overall thickness of the semiconductor package since the package should adequately protect the wire as it loops from the die to leads. For example, the shorter the loop height, the thinner the package can be constructed.
The wire loop height can be reduced to about 0.003 inches by the use of an entirely different wiring technique know as tab bonding (“tape automated bonding”). However, tab bonding is uneconomic due to the high cost of the materials required and the necessity to have custom film for each different die. The extra processing required in a tab bonding also results in diminished yields.
Known thin semiconductor packages, such as TQFPs, mBGAs, and CSPs, using wire bonding only use dies with an “in-line bond pad layout” or a “single row bond pad layout” such that only one row of bond pads is located at the periphery of the die. On the other hand, multiple row bond pad layouts, such as staggered bond pad layouts or aligned multiple row bond pad layouts, are particularly problematic in such thin packages due to the loop heights of the wires. For example, a staggered bond pad layout typically consists of an outer row of bond pads and an inner row of bond pads in parallel to the outer row of each other on the surface of the die. The outer row of bond pads is typically located at the periphery of the die or chip while the inner row of bond pads is typically located parallel to the outer row, but located farther away from the periphery of the die while the individual inner bond pads are staggered from the individual outer bond pads. As is conventionally done, each bond pad of the inner and outer row is interconnected with a respective lead of the lead frame, or substrate in a BGA package, by forming a ball bond at the respective bond pads of the die using a capillary as known in the art. Thus, the outer bond pads have a ball bond with a wire extending from it, which is looped over to the leads forming a wire loop having a first loop height. However, the inner bond pads also have a ball bond with a wire extending therefrom forming wire loops over to respective leads of the lead frame or substrate. The wire loop extending from each of the inner bond pads to the leads must form a higher loop height (i.e. a second loop height) in order to clear the wire loops connected from the outer bond pads to the leads. This additional loop height may as much as double the overall loop height of the wire bonds. Thus, if staggered bond pad layouts or similar multiple row bond pad layouts are used in the thin semiconductor packages mentioned above, the wires connecting the inner bond pads to the leads may be exposed to the exterior of the semiconductor package. The additional loop height (i.e. the second loop height) for wire loops attached at the inner row of bond pads increases the overall thickness needed for the package to adequately protect the die and the wire interconnects. As such, wire bonded staggered bond pad layouts, and other bond pad layouts involving multiple rows of bond pads that use wire bonding, are not found in thin semiconductor packages, such as TQFPs, mBGAs, and CSPs.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a method, and an electrical interconnection formed using the method, for reducing the wire loop height while forming wire bonds between bond pads of multiple row bond pad layout dies, e.g. staggered bond pad layout dies, and other bonding locations, e.g. the leads.
In one embodiment, the invention can be characterized as a method of forming a low loop height wire interconnection in a semiconductor package including a die having a multiple row bond pad layout comprising the steps: forming a first ball bond from a first wire at a first bonding location; looping the first wire to a first bond pad of a die; forming a first stitch bond between the first wire and the first bond pad; forming a second ball bond from a second wire at a second bond pad of the die; looping the second wire to a second bonding location, wherein the second wire does not contact the first wire; and forming a second stitch bond between the second wire and the second bonding location.
In another embodiment, the invention can be characterized as an electrical wire interconnection system for a semiconductor package having a multiple row bond pad layout. The system includes a first row of bond pads and a second row of bond pads located on the die. A stitch bond is formed at each of one or more of the first row of bond pads between respective wires and the one or more of the first row of bond pads. And a ball bond is formed at each of one or more of the second row of bond pads between other respective wires and the one or more of the second row of bond pads.
In a further embodiment, the invention can be characterized as an electrical wire interconnection of a semiconductor package comprising a lead interconnection, such as a lead frame or substrate, including a plurality of leads. A stitch bond is formed at one of the plurality of leads between a first wire coupled to a die and the one of the plurality of leads. And a ball bond is formed at another one of the plurality of leads between a second wire coupled to the die and the other one of the plurality of leads.
REFERENCES:
patent: 5311057 (1994-05-01), McShane
patent: 5328079 (1994-07-01), Mathew et al.
patent: 5558267 (1996-09-01), Humphrey et al.
patent: 6031216 (2000-02-01), Singh et al.
Low Qwai H.
Ranganathan Ramaswamy
Torcuato Rey
Elms Richard
LSI Logic Corporation
Smith Bradley
LandOfFree
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