Multiple reaction chamber system having wafer recognition...

Details Multiple reaction chamber system having wafer recognition... Multiple reaction chamber system having wafer recognition...

1998-09-25

2001-05-22

Grant, William (Department: 2121)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S115000, C700S116000, C700S215000, C700S221000, C414S936000

Reexamination Certificate

active

06236903

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiple reaction chamber system and a method of processing a wafer using the same, and more particularly, to a multiple reaction chamber system having an individual wafer recognition system, and a method of processing a wafer using the same.
2. Description of the Related Art
Because modem, highly integrated semiconductor devices are complicated to manufacture, manufacturing productivity can be increased by converting a single reaction chamber system into a multiple reaction chamber system.
As shown in
FIG. 1
, a conventional multiple reaction chamber system
26
includes a transfer chamber
10
and a plurality of other chambers connected to the transfer chamber
10
. More specifically, first and second load lock chambers
12
and
14
, and an align chamber
16
having a wafer aligner
16
a
for aligning wafers, are connected to the transfer chamber
10
. First and second reaction chambers
18
and
20
are also connected to the transfer chamber
10
. Each chamber is closed to prevent wafers from being exposed to air.
In
FIG. 1
, solid line arrows A, dashed line arrows B and dotted line arrows C indicate the various paths for moving a wafer among the chambers.
A wafer loaded in either the first or second load lock chamber
12
or
14
, for example, the first load lock chamber
12
, is transferred to the align chamber
16
along one of the solid line paths A. After the wafer is aligned in the align chamber
16
, the wafer is transferred to either the first or second reaction chamber
18
or
20
, for example, the first reaction chamber
18
, along one of the other solid line paths A. The reaction chamber
18
or
20
, for example, the first reaction chamber
18
, processes the wafer. Then, the wafer is transferred to the first load lock chamber
12
via the transfer chamber
10
along one of the dashed line paths B, or to the second load lock chamber
14
via the transfer chamber
10
along one of the dotted line paths C. The other wafers loaded in the first and second load lock chambers
12
and
14
are also handled through the same alternative paths as the first selected wafer.
When a wafer is not properly processed due to a malfunction of the first reaction chamber
18
, the second reaction chamber
20
should be used instead of the first reaction chamber
18
. However, when the conventional multiple reaction chamber system is used the previous paths are simply repeated. Thus, some wafers will continue to be processed in the malfunctioning reaction chamber. Accordingly, the wafer processing process continues until inferior wafers are detected among the processed wafers. Furthermore, even when inferior wafers are detected, it is not known which reaction chambers they were processed in. Thus, a lot of time is required to solve the problem, so that productivity of the semiconductor device manufacturing facility is lowered.
SUMMARY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide a multiple reaction chamber system comprising a wafer recognition system for easily recognizing which wafer is being processed in which reaction chamber and matching a processed wafer with a reaction chamber.
It is another object of the present invention to provide a method of processing wafers using the multiple reaction chamber system.
Accordingly, to achieve these objects and other objects and advantages of the present invention, a multiple reaction chamber system includes a transfer chamber, a load lock chamber connected to the transfer chamber, and a plurality of reaction chambers connected to the transfer chamber. An alignment chamber is connected to the transfer chamber, disposed along a path of wafer transfer from the load lock chamber to the plurality of reaction chambers, and includes a wafer aligner. A wafer recognition system, having means for recognizing an identification code of an individual wafer, is disposed along a post-aligner portion of the path of wafer transfer. A controlling system is in data communication with the wafer recognition system for selecting a designated chamber of the plurality of reaction chambers into which the individual wafer is to be transferred.
In another aspect of the invention, a method for processing wafers in a multiple reaction chamber system includes forming a recognition code on a wafer. Then the wafer is loaded into a load lock chamber of the multiple reaction chamber system having a plurality of reaction chambers and an alignment chamber. The wafer is transferred into the alignment chamber and aligned. A wafer recognition system recognizes the recognition code on the wafer. Next, it is decided which one of the plurality of reaction chambers is to process the wafer, and the wafer is processed in the selected one of the plurality of reaction chambers. After this processing, the wafer is inspected.
The present invention provides data that can be managed according to wafers and reaction chambers. Thus, it can be accurately recognized which wafer was processed in which reaction chamber during processing, and therefore which chamber is producing defective wafers, if any. Based on this, a controlling system can prevent wafers from being processed in a malfunctioning reaction chamber, and thus reduce unnecessary operations. Therefore, reliability and productivity of the semiconductor device manufacturing facility can be improved.


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