Multiple power line arrangement for a semiconductor memory devic

Details Multiple power line arrangement for a semiconductor memory devic Multiple power line arrangement for a semiconductor memory devic

1996-12-04

1998-05-05

Le, Vu A.

Static information storage and retrieval

Powering

365 51, 365 63, 257774, 257758, 257776, 257206, 257207, 257208, 257211, H01L 2710

Patent

active

057485500

ABSTRACT:
A method and system for arranging power lines of a semiconductor memory device in order to prevent cracking of the power lines and to reduce resistance of the power lines without the provision of slits in the power lines. A first metal and a second metal for a first power line are connected to each other by contacting the first metal with the second metal; a first metal and a second metal for a second power line are also connected to each other by contacting the first metal with the second metal; the first metal for the first power line and the first metal for the second power line are arranged adjacent to each other; the second metal for the first power line and the second power line for the second power line are also arranged adjacent to each other; and the second metal of the first power line partially overlaps both the first metal for the first power line and the first metal for the second power line. No slits are provided between the first metals for the first and second power lines and the second metals therefor.

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