Multiple ports memory-cell structure

Details Multiple ports memory-cell structure Multiple ports memory-cell structure

2001-01-26

2002-06-11

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189110

Reexamination Certificate

active

06404670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high performance semiconductor memory devices, and more particularly to embedded memory devices having first level bit lines connected along different layout directions. This invention is further related to circuit configurations and novel techniques for enabling multiple ports reading and writing operations for memory arrays.
2. Description of the Prior Art
DRAM is usually considered as a high density, low cost, but low performance memory device. DRAM's of current art always have lower performance relative to other types of semiconductor memories such as static random access memory (SRAM). The density of DRAM has been improved rapidly; the extent of integration has been more than doubled for every generation. Such higher integration of DRAM has been realized mainly by super fine processing technique and improvements in memory cell structure. In the mean time, the improvement in DRAM performance is progressing at a much slower rate. This relatively slower improvement rate in performance generates a performance gap between logic devices and memory devices. Many new approaches have been proposed to reduce this performance gap. The synchronized DRAM (SDRAM), the extended data output (EDO) DRAM, the multiple bank DRAM (MDRAM), and the RAMBUS system approaches are the most well known methods to improve DRAM performance. U.S. Pat. No. 4,833,653 issued to Mashiko et al. and U.S. Pat. No. 4,758,993 issued to Takemae et al. disclosed DRAM having selectively activated subarrays in order to improve performance. Another approach to improve DRAM performance is to place an SRAM cache into DRAM (called “hybrid memory”). U.S. Pat. No. 5,421,000 issued to Fortino et al., U.S. Pat. No. 5,226,147 issued to Fujishima et al., U.S. Pat. No. 5,305,280 issued to Hayano et al. disclosed embodiments of hybrid memories. The major problem for above approaches is that they are paying very high price for performance improvement, while the resulting memory performance improvement is still not enough to fill the gap. Another problem is that all of those approaches require special system design that is not compatible with existing computer systems; it is therefore more difficult to use them in existing computer systems.
In U.S. Pat. No. 6,061,268, Kuo et al. disclose a two-port six-transistor (6T) static random access memory (SRAM) cell structure with single-bit-line simultaneous read-write access capability using partially depleted silicon on insulator (SOI) CMOS dynamic threshold technique. In yet another U.S. Pat. No. 6,118,689 Kuo et al. disclose a two-port six-transistor SRAM cell with single-bit-line simultaneous read-and-write access capability. The source terminal of an NMOS device in the SRAM cell is connected to the write word line.
FIG. 1A
is a diagram for showing a SRAM disclosed by Kuo et al. that provides two port simultaneous read-and-write accesses. Kuo's structure is limited by access capability that one of bit-lines can be employed only for a read operation and another bitline only for a writing operation. In order to gain more flexibility to read and write from both ports, another set of bit-lines has to be added as that shown in
FIG. 1B. A
dual port structure as shown in
FIG. 1B
occupies larger areas and becomes more complex in structure and less desirable. Even for a most basic single-port read/write operation, two bit-lines and one wordline, as that shown in
FIG. 1C
is required. As the size of a memory array is increased, these additional bitline occupies large areas and becomes a major design constraint to more a effective area utilization.
Another disadvantage of DRAM is the need to refresh its memory. That is, the users need to read the content of memory cells and write the data back every now and then. The system support for DRAM is more complex than SRAM because of this memory refresh requirement. Memory refresh also represents a waste in power. U.S. Pat. No. 5,276,843 issued to Tillinghast et al. discloses a method to reduce the frequency of refresh cycles. U.S. Pat. No. 5,305,280 issued to Hayano et al. and U.S. Pat. No. 5,365,487 issued to Patel et al. disclosed DRAM's with self-refresh capability. Those inventions partially reduce power consumption by refresh operations, but the magnitude of power saving is very far from what we can achieve by the present invention. The resource conflict problem between refresh and normal memory operations also remains unsolved by those patents.
Recently, Integrated Device Technology (IDT) announced that the company could make DRAM close to SRAM performance by cutting DRAM into small sub-arrays. The new device is not compatible with existing memory; it requires special system supports to handle conflicts between memory read operation and memories refresh operation. It requires 30% more area the DRAM, and its performance is still worse than SRAM of the same size.
Another important problem for DRAM design is the tight pitch layout problem of its peripheral circuits. In the course of the rapid improvement in reducing the size of memory cells, there has been no substantial improvement or change as to peripheral circuits. Peripheral circuits such as sense amplifiers, decoders, and precharge circuits are depend upon memory cell pitch. When the memory cells are smaller for every new generation of technology, it is more and more difficult to “squeeze” peripheral circuits into small pitch of memory layout. This problem has been magnified when the memory array is cut into smaller sub-arrays to improve performance. Each subarray requires its own peripheral circuits; the area occupied by peripheral circuits increases significantly. Therefore, in the foreseeable future, there may occur a case wherein the extent of integration of DRAM is defined by peripheral circuits. U.S. Pat. No. 4,920,517 issued to Yamauchi et al. disclosed a method to double the layout pitch by placing sense amplifiers to both ends of the memory. This method requires additional sense amplifiers. Although the available layout pitch is wider than conventional DRAM, the layout pitch is still very small using Yamauchi's approach.
All of the above inventions and developments provided partial solutions to memory design problems, but they also introduced new problems. It is therefore highly desirable to provide solutions that can improve memory performance without significant degradation in other properties such as area and user-friendly system support.
Another difficulty encountered by those of ordinary skill in the art is a limitation that Dynamic Random Access Memory (DRAM) which is usually considered as a high density, low cost, and low performance memory device cannot be conveniently integrated as embedded memory. This is due to the fact that higher integration of DRAM has been realized mainly by super fine processing technique and improvements in memory cell structure. A typical DRAM manufacture technology of current art is the four layer poly silicon, double layer metal (4P2M) process. Such memory technology emphasizes on super-fine structure in manufacture memory cells; performance of it logic circuit is considered less important. A technology optimized to manufacture high speed logic products have completely different priority; it emphasizes on performance of transistors, and properties of multiple layer metals. An example of a typical logic technology of current art is the triple layer metal, single poly silicon (1P3M) technology.
An embedded memory, by definition, is a high density memory device placed on the same chip as high performance logic circuits. The major challenge to manufacture high density embedded memory is the difficulty in integrating two types of contradicting manufacture technologies together. An embedded technology of current art requires 4 layers of poly silicon and 3 layers of metal. There are more than 20 masking steps required for such technology. It is extremely difficult to have reasonable yield and reliability from such complex technology of cur

Affiliated with

Also associated with

Rating

Multiple ports memory-cell structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple ports memory-cell structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple ports memory-cell structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2956469