Multiple-port ring buffer

Details Multiple-port ring buffer Multiple-port ring buffer

1999-02-19

2000-04-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523003, 365238, A11C 700

Patent

active

060523123

ABSTRACT:
A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an internal memory and/or an external display memory. Each MPRB comprises a plurality of addressable storage location holding video data and linked in a logical ring configuration. In addition, each MPRB has at least three ports, selected from write ports for writing to the addresses of the storage locations and read ports for reading from the addresses. Each read port in the MPRB is disposed a certain distance, or number of storage locations, behind a write port. This distance defines the size of the memory emulated by the MPRB. By positioning multiple read ports at different distances from the write ports, a single MPRB can emulate several different memories of different sizes. Since a write port needs to write the video data to the MPRB only once and the data need not be moved within the MPRB, the memory bandwidth consumed by the MPRB is substantially less than that required by the discrete memories.

REFERENCES:
patent: 3772658 (1973-11-01), Sarlo
patent: 4303986 (1981-12-01), Lans

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