Multiple port memory with prioritized world line driver and...

Details Multiple port memory with prioritized world line driver and... Multiple port memory with prioritized world line driver and...

2007-02-19

2009-12-08

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S191000, C365S195000, C365S230060, C365S230080, C365S233100

Reexamination Certificate

active

07630272

ABSTRACT:
A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.

REFERENCES:
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patent: 6151266 (2000-11-01), Henkels et al.
patent: 6169700 (2001-01-01), Luo

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