Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-03-19
2003-09-30
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C707S793000
Reexamination Certificate
active
06629215
ABSTRACT:
PRIOR FOREIGN APPLICATION
This application claims priority from European patent application number 00105819.7, filed Mar. 20, 2000, which is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
This invention relates to a multiple port memory apparatus, a method of operating a multiple port memory apparatus, an out-of-order processing apparatus comprising such memory apparatus, a data processing system comprising said out-of-order processing apparatus and a data processing system carrying out said method.
BACKGROUND ART
A multiple port memory comprises a plurality of ports. Such memory can be a random access memory (RAM) or a static random access memory (SRAM). Generally, each port represents an independent input and/or output path for writing data into the memory. A multiple port memory may, for example, comprise several write ports and read ports but the number of write ports need not to be the same as the number of read ports.
When attempting to increase the number of the write ports of a multiple port memory, the complexity of the wiring and the percentage of the area needed for the wiring with regard to the total area needed for the memory cell transistors and the wiring grows with the square to the number of the ports.
Particularly, in data processors comprising a plurality of multiple port memories, multiple port registers or multiple port arrays, the die area occupied by the memories, registers or arrays comprising a large number of ports is usually determined by the area needed for wiring rather than by the area needed for the transistors forming them.
Therefore, there is a need for an improved wiring management approach for multiple port registers and multiple port memory arrays.
SUMMARY OF THE INVENTION
In order to reduce the chip area needed when increasing the number of the write ports of a multiple port memory array with K write ports and L read ports (K=2, 3, 4, . . . and L=1, 2, 3, . . . ), the present invention proposes to substitute such a multiple port memory array by two or more multiple port memory arrays and a selection device. The two or more multiple port memories are chosen to comprise in total K write ports and each multiple port memory array comprises a subset of the total numbers of write ports and L read ports.
In a preferred embodiment of the invention, the two or more multiple write port memory arrays all comprise the same number and the same addresses available for writing data into them. Since it has to be determined, whether first data written into a specific address of a first multiple port memory array are younger or older than second data written into the same specific address but of a second or further multiple port memory array, the invention proposes to use a selection device. The selection device according to the invention stores for each available address for the two or more multiple port memory arrays, into which of them data have been lastly written.
In another preferred embodiment of the invention, the selection device comprises a multiple port memory array. Preferably, the multiple port memory array of the selection device comprises the same number of addresses and the same addresses as each of the two or more multiple port memory arrays for data storage, wherein the two or more multiple port memory arrays are preferably all the same.
In a further preferred embodiment of the invention, each write port of the memory array of the selection device is connected with a different write port of the two or more multiple port memory arrays and the one or more addresses applied to the two or more multiple port memory arrays at one or more write cycles is also applied to the multiple port memory array of the selection device. The selection device stores one or more control bits under the address applied to its one or more address inputs indicating via which write port of the two or more multiple port memory arrays and/or into which memory array data have been written at last into the specific address of the two or more multiple port memory arrays. For example, if the multiple port memory apparatus according to the invention comprises two multiple port memory arrays for data storage, only a single control bit either with a high-level or a low-level has to be stored for each address of the two multiple port memory arrays. The single control bit is stored in the memory array of the selection device and allows to indicate into which of the two multiple port memory arrays data have been written at last for a specific address. Accordingly, the storage capacity of the memory array of the selection device per address comprises only a single bit.
It will be understood that the storage capacity per address has to be enlarged to two or more control bits, if more than two multiple port memory arrays are used, in order to be able to indicate by the stored control bits into which of the more than two multiple port memory arrays for data storage data have been lastly written.
In yet a further preferred embodiment of the invention, the selection device of the multiple port memory apparatus according to the invention comprises a set of multiplexers. The inputs of each of the multiplexers are connected with a read port of the different multiple port memory arrays for data storage and a further select input of each of the multiplexers is connected with a different read port of the memory array of the selection device. When applying the one or more control bits to the select input of each of the multiplexers during a read process, the control bits control each multiplexer to output only the data stored in the two or more multiple port memory arrays for data storage for a specific address, which have been lastly written.
The above summary of the present invention is not intended to describe each embodiment or every implementation of the present invention. Advantages and attainments, together with a more complete understanding of the invention, will become apparent and appreciated by referring to the following detailed description and claims taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4916700 (1990-04-01), Ito et al.
patent: 4933879 (1990-06-01), Ando et al.
patent: 5359557 (1994-10-01), Aipperspach et al.
patent: 5428575 (1995-06-01), Fudeyasu
patent: 5600834 (1997-02-01), Howard
patent: 5991186 (1999-11-01), Balistreri et al.
patent: 6125371 (2000-09-01), Bohannon et al.
Lattimore George M.
Pille Juergen
Sautter Rolf
Wendel Dieter
Augspurger, Esq. Lynn L.
Heslin Rothenberg Farley & & Mesiti P.C.
Nguyen Hiep T.
Schiller, Esq. Blanche E.
LandOfFree
Multiple port memory apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple port memory apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple port memory apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3107241