Multiple port cells with improved testability

Details Multiple port cells with improved testability Multiple port cells with improved testability

1995-01-19

1996-07-30

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Multiple port access

36523006, 36523008, 365239, 365194, G11C 700

Patent

active

055418872

ABSTRACT:
Sequentially terminated write enable pulses applied to respective input ports of a multi-port memory cell is effective to establish a priority among those input ports and provide unconditionally unambiguous writing to a memory cell when write operations are concurrently attempted at two or more ports of that cell, as may be encountered during rigorous testing procedures. Memory structure, particularly that of the input port circuits, is simplified and operational speed is enhanced since signal propagation through a comparator or logic circuit is avoided. Time required for testing of large memory arrays is also significantly reduced.

REFERENCES:
patent: 5434818 (1995-07-01), Byers et al.

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