Multiple phase-locked loop circuit

Details Multiple phase-locked loop circuit Multiple phase-locked loop circuit

2002-02-19

2004-09-14

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C375S374000, C327S148000, C327S157000, C331SDIG002

Reexamination Certificate

active

06792064

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiple phase-locked loop (PLL) circuit having a function of preventing a deadlock.
The present application claims priority of Japanese Patent Application No. 2001-044337 filed on Feb. 20, 2001 which is hereby incorporated by reference.
2. Description of the Related Art
Generally, in a conventional multiple PLL circuit, as explained in detail later, an UP signal used to increase an oscillation frequency and a DN signal used to lower the oscillation frequency are output from a phase/frequency comparator adapted to detect a difference in phase between a reference signal and a feedback signal obtained by dividing a frequency of an oscillation signal output from a voltage controlling oscillator (VCO). Then, an error signal produced based on each of pulse widths of the UP signal and DN signal is output from a charge pumping circuit. A control signal being at a level corresponding to that of the error signal is output through a low pass filter (LPF), which controls the oscillation signal output from the voltage controlling oscillator to cause the oscillation frequency to match the frequency of the reference signal, thus causing the oscillation signal to be synchronized with the reference signal.
Hereinafter, configurations and operations of the conventional multiple PLL circuit will be described by referring to FIG.
9
. As shown in
FIG. 9
, the conventional multiple PLL circuit chiefly includes a phase/frequency comparator (PFD)
1
, a charge pumping (CP) circuit
2
, a low pass filter (LPF)
3
, a voltage controlling oscillator (VCO)
4
, and a frequency divider (DIV)
5
.
The PFD
1
compares a phase or a frequency of a signal input to an input terminal S
1
with a phase or a frequency of another signal input to an input terminal S
2
and, if the other signal input to the input terminal S
2
lags the signal input to the input terminal S
1
or if the frequency of the other signal input to the input terminal S
2
is lower than that of the signal to the input terminal S
1
, outputs an UP signal being a pulse which falls by a rise of the signal input to the input terminal S
1
and rises by a rise of the other signal input to the input terminal S
2
, to an output terminal “u” and further, if the other signal input to the input terminal S
2
leads the signal input to the input terminal S
1
or if the frequency of the other signal input to the input terminal S
2
is higher than that of the signal input to the input terminal S
1
, outputs a DN signal being a pulse which rises by a rise of the other signal input to the input terminal S
2
and falls by a rise of the signal input to the input terminal S
1
.
The CP circuit
2
, by generating an error signal to be output from an output terminal “e” in response to an UP signal input to an input terminal L
1
and in response to a DN signal input to an input terminal L
2
, operates so as to cause a current to flow out from a power source through the output terminal “e” or a current to flow to a ground from the output terminal “e”. The LPF
3
, by removing a high frequency component based on the flow-in and flow-out of currents contained in the error signal fed from the charge pumping circuit
2
, generates a smoothed control signal. The VCO
4
generates an output clock signal a frequency of which changes to be high or low depending on whether a control voltage is large or small. The DIV
5
outputs a frequency-divided clock signal div.CLK obtained by dividing a frequency of an output clock signal VCO.CLK output from the VCO
4
.
The conventional PFD
1
, as shown in
FIG. 10
, includes inverters
1
A,
1
B,
1
M,
1
N,
1
P,
1
R to
1
T,
1
V to
1
Y, NAND gates
1
C to
1
H,
1
J,
1
K, NOR gates
1
L,
1
Q, and
1
U. Of them, the NAND gates
1
D and
1
E make up a first flip-flop and the NAND gates
1
G and
1
H make up a second flip-flop. Moreover, the NOR gate
1
Q and the inverters
1
R and
1
S make up a reset circuit.
A reference clock signal ref.CLK input to the input terminal S
1
is fed through the inverter
1
A to the NAND gate IC. The NAND gate IC computes the NAND of the reference clock signal ref.CLK with a previous output signal and outputs a result of the computation to the NAND gate
1
F. The NAND gate
1
F computes the NAND of an output of the first flip-flop with an output from the NAND gate
1
C and produces a signal
1
a
from a result of the computation. Moreover, the frequency-divided clock signal div.CLK output from the DIV
5
and input to the input terminal S
2
is fed through the inverter
1
B to the NAND gate
1
J. The NAND gate
1
J computes the NAND of the frequency-divided clock signal div.CLK with a previous output signal and outputs a result of the computation to the NAND gate
1
K. The NAND gate
1
K computes the NAND of an output from the second flip-flop with an output from the NAND gate
1
J and produces a signal
1
b
from a result of the computation.
The signal
1
a
is a signal generated based on the reference clock signal ref.CLK and its duty ratio is fixed, while the signal
1
b
is a signal generated based on the frequency-divided clock signal div.CLK obtained by dividing the output clock signal VCO.CLK using the DIV
5
and its duty ratio changes depending on a phase difference between the frequency-divided clock signal div.CLK and reference clock signal ref.CLK.
The signal
1
a
is output to the NOR gate
1
L. The NOR gate
1
L computes the NOR of a reset signal fed from the reset circuit with the signal
1
a
and outputs a result of the computation to the inverter
1
M. The inverter
1
M inverts the output from the NOR gate
1
L to produce an output signal. The output from the inverter
1
M is input to the NAND gate
1
C and is also output as an UP signal to output terminal “u” through inverters
1
N and
1
P.
Also, the signal
1
b
is output to the NOR gate
1
U. The NOR gate
1
U computes the NOR of the reset signal from the reset circuit with the signal
1
b
and outputs a result of the computation to the inverter
1
V. The inverter
1
V inverts the output from the NOR gate
1
U to generate an output signal. The output signal from the inverter
1
V is output to the NAND gate
1
J and through the inverters
1
W,
1
X, and
1
Y to an output terminal “d” as a DN signal.
A relation between the UP signal and DN signal is described below. That is, if the frequency-divided clock signal div. CLK to be input to the input terminal S
2
lags the reference clock signal ref.CLK to be input to the input terminal S
1
or if a frequency of the frequency-divided clock signal div.CLK to be input to the input terminal S
2
is lower than that of the reference clock signal ref.CLK to be input to the input terminal S
1
, as shown in FIG.
11
, during a period of time from a rise of the reference clock signal ref.CLK input to the input terminal S
1
to a rise of the frequency-divided clock signal div.CLK input to the input terminal S
2
, the UP signal being a downward pulse as shown by being hatched in
FIG. 11
is output to the output terminal “u”. During this period, no DN signal is output to the output terminal “d”.
Moreover, if the frequency-divided clock signal div. CLK to be input to the input terminal S
2
leads the reference clock signal ref.CLK to be input to the input terminal S
1
or if a frequency of the frequency-divided clock signal div. CLK to be input to the input terminal S
2
is higher than that of the reference clock signal ref.CLK to be input to the input terminal S
1
, as shown in
FIG. 12
, during a period of time from a rise of the frequency-divided clock signal div.CLK input to the input terminal S
2
to a rise of the reference clock signal ref.CLK input to the input terminal S
1
, the DN signal being an upward pulse as shown by being hatched in
FIG. 12
is output to the output terminal “d”. During this period, no UP signal is output to the output terminal “u”.
The CP circuit
2
, by generating an error signal in response to the UP signal or DN signal output from the PFD
1
, charges or discharges the L

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