Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2007-09-18
2007-09-18
Lee, Eugene (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S628000, C257S301000, C257S302000, C257S296000, C257S300000, C257SE29003
Reexamination Certificate
active
10929281
ABSTRACT:
Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2on a top surface of a silicon wafer and a trench layer of SiO2on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.
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Forbes Leonard
Noble Wendell P.
Lee Eugene
Schwegman Lundberg Woessner & Kluth P.A.
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