Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2002-05-06
2004-10-05
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S302000, C257S627000, C438S198000, C438S270000
Reexamination Certificate
active
06800927
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits. In particular, the present invention relates to a method and structure for oxide thicknesses on Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology for merged memory and logic applications.
BACKGROUND OF THE INVENTION
Typically, memory, e.g., Dynamic Random Access Memory (DRAM), and logic technologies have evolved along separate but parallel paths. In memory technology, for any particular lithography and power supply voltage level generation, the gate oxide thickness is limited by thin oxide reliability due to the stress of voltage boosted word lines. In contrast, for logic technology, thinner gate oxide thicknesses are generally the standard because of the need for high transconductance at lower internal operating voltages. Therefore, efforts to merge the technologies of memory and logic onto a single chip to create a “system on a chip” or other high function memory thus create a dilemma. That is, one is faced with the design choice of either (1) compromising the gate oxide thickness for one and/or both types of devices or (2) assuming the litany of complexities and expenses associated with the growing of two separate types of gate oxides on a single chip.
One current approach has been proposed that does provide a method of fabrication which allows for the scalable gate oxide thicknesses by either implanting Ar
+
or N
+
into a substrate prior to oxidation or implanting O
+
into the substrate after gate deposition. While this approach does facilitate gate oxide scalability when compared to conventional process integration, this technique does not provide a total solution since additional steps as well as expensive process tools are required. Accordingly, more advanced methods are still needed for providing multiple gate oxide thicknesses on a single chip. Desirably these more advanced methods will use existing MOSFET and DRAM processing techniques, thus avoiding any additional complexity in the wafer fabrication process. For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory and logic technologies and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are described which accord improved benefits for merged memory and logic applications.
Improved methods and structures are provided for multiple oxide thickness on a single silicon wafer. In particular, improved methods and structures are provided for multiple gate oxide thickness on a single chip which includes circuitry encompassing a range of technologies. For example, this range of technologies can include but is not limited to the memory and logic technologies. Moreover, these improved methods and structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.
Embodiments of a method for forming a semiconductor device include forming a top layer of SiO
2
(silicon dioxide) on a top surface of a silicon wafer. A trench layer of SiO
2
is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order crystal plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO
2
are such that a thickness of the top layer is different from a thickness of the trench layer.
One method of the present invention provides for forming a semiconductor device. Another method includes forming a DRAM that can include a trench capacitor or a stacked capacitor. Moreover, other embodiments provide for forming a Non-Volatile Random Access Memory (NVRAM) device, a flash memory device as well as a programmable logic array. The present invention also includes systems incorporating these different devices and circuits all formed according to the methods provided in this application.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
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Forbes Leonard
Noble Wendell P.
Cuneo Kamand
Kilday Lisa
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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